[SOLVED] Multiplier on VHDL explanation

[Vhdlontherise]

Hi everyone, i am facing a problem with a project in VHDL.
Part of the task is to implement a series of components that are each composed by a multiplier, developed with a behavioural architecture. This one receive two inputs but these are not always available at the same moment for every component.
Does VHDL syntax have a word to make my component wait for both inputs to be available? Being "a" and "b" the inputs i tried with different conditions but it won't work.
I tried for example with "a'event", "b'event", "a'event and b'event", i even tried with different conditions with nested if-sentences such as "if( a'event and b /= "U") then - if(b'event and a/="U")" (in my code the words have 8 bit so this latest one is a little bit different but it is just to give an idea).
I'll share a pic of my code for the multiplier and the wave form of the signals.
As you can see, since the input "s_a_molt" is available and "s_b_molt" is not, it doesn't calculate the result. (of course).
Thanks for your time

 

[wwfeldman]

maybe this logic will help:

wait for a event or b event (since no apparent reason that a will always come first)
specify appropriate temporary variable (a or b, whichever came first)
wait for other event
specify appropriate temporary variable.
multiply

there's something i'm missing. probably because i'm not familiar with behavioral models in vhdl
is this a routine that sits and waits for something to happen, or is it activated by an interrupt?
if the former, i see no loops or other structure to allow for waiting
if the later, wouldn't you need two interrupt handlers, one for event a and one for event b,
set appropriate flags in each, and multiply when you've got a and b?

 

[FvM]

The only event that can be used in synthesizable VHDL is a clock edge. Other events exist only in simulation.

Honestly I don't understand which problem you are trying to solve here. In a clocked design, signals don't change at arbitrary times. Are you dealing with asynchronous input signals?

 

[kaz1]

The question is bizarre. If you don't have inputs ready you can keep multiplier generating outputs and ignore result until it is valid.

 

[Vhdlontherise]

Hi everyone, thanks for your contribution.
The inputs are not sync to a clock, since i have a serie of components if i control them with a clock signal some of them do the calculations on the same inputs, that's why i am controlling the multipliers with conditions that check if the inputs change.
I am going to attach a picture: you can see the inputs/outputs of two multiplier, one gives the correct answer while the other don't.
The first one is related with the first three values while the second one with the last three.
As you can see when the input "s_b_molt" is available before "s_a_molt" the component gives the correct answer, while when "s_a_molt" is already available and "s_b_molt" comes after, the answer is undefined.
This is because in the if-statement i imposed to calculate the product only if "a" changes its value... my problem is how to make the multiplier to wait on both inputs to be available. (I tried also with "if((s_a_molt'event) and (s_b_molt'event)) then ..." but in some of my serie of multipliers the inputs are available at the same time or it is available before "a" than "b") .
It can be solved with a check on the output but i don't know how to do that. I tried like i did in the second picture that i am going to attach.
Thanks again to everyone!

 

[kaz1]

You can use enable signal at any module to enable/disable when you want it.

if enable then
y <= A*B
...