module fir9 (
output logic signed [10:0] y,
input logic signed [3:0] x,
input logic signed [4:0] c [0:8],
input logic rst,
input logic clk);
logic signed [4:0] x_delay [0:8];
logic signed [8:0] mult [0:8];
always_ff@(posedge clk) begin
if(rst) begin
for(int i=0; i<9; i++) begin
x_delay[i] <= 0;
mult[i] <= 0;
end
y <= 0;
end else begin
x_delay[0] <= x;
for(int i=1; i<9; i++) x_delay[i] <= x_delay[i-1];
for(int i=0; i<9; i++) mult[i] <= x_delay[i] * c[i];
y <= mult[0] + mult[1] + mult[2] + mult[3] + mult[4] + mult[5] + mult[6] + mult[7] + mult[8];
end
end
endmodule