Need help with abnormal reset behavior in synthesis.

[BartlebyScrivener]

I am designing a 9 tap fir filter to learn how to synthesize SystemVerilog code using Quartus. My code works in simulation and synthesizes however when I look at the RTL viewer it appears that instead of connecting my signal `rst` to the reset of each DFF, it connects `rst` to the select of a multiplexer and multiplexes the input to my registers with 0s!

Is there some particular rst design I am missing?

module fir9 (
  output logic signed [10:0] y,
   input logic signed [3:0] x,
   input logic signed [4:0] c [0:8],
   input logic rst,
   input logic clk);
   

      logic signed [4:0]  x_delay [0:8];
      logic signed [8:0]  mult [0:8];
 

  always_ff@(posedge clk) begin
    if(rst) begin
      for(int i=0; i<9; i++) begin 
        x_delay[i] <= 0;
        mult[i] <= 0;
      end
      y <= 0;
    end else begin
      x_delay[0] <= x;
      for(int i=1; i<9; i++) x_delay[i] <= x_delay[i-1];
      for(int i=0; i<9; i++) mult[i] <= x_delay[i] * c[i];
      y <= mult[0] + mult[1] + mult[2] + mult[3] + mult[4] + mult[5] + mult[6] + mult[7] + mult[8];
    end
  end

endmodule

 

[TrickyDicky]

This is because the registers in Altera devices dont have a synchronous reset input, so sync reset functionality has to be emulated via a mux. The reset input on the flops is an async reset, which can be used safeuly if that signal is synchronised.