Need Help: Nothing in layout

[joman]

nothing in layout

Dear all:

I got those message

It can't run lvs, and wrong message are "Corresponding cells could not be identified"

But I use another account, it still worked!

What can I do?

Thank you!


===========================================

OVERALL COMPARISON RESULTS



# # ########################
# # # #
# # NOT COMPARED #
# # # #
# # ########################


Error: Nothing in layout.



**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************


o LVS Setup:

// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "HVDD"
LVS GROUND NAME "VEE"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS EXPAND SEED PROMOTIONS YES
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS NO
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM ALL
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTION AB AC AD F G J L RB RC RD RE RF RG YB
LVS REPORT OPTION A B C D E S
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE

// Device Type Map

LVS DEVICE TYPE RESISTOR "RNHRPO_EHV320" SOURCE LAYOUT
LVS DEVICE TYPE RESISTOR "RNPPO_EHV320" SOURCE LAYOUT
LVS DEVICE TYPE RESISTOR "RNNPO_EHV320" SOURCE LAYOUT
LVS DEVICE TYPE CAPACITOR "MIMCAPS_EHV" SOURCE LAYOUT

// Reduction

LVS REDUCE SERIES MOS NO
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCTION PRIORITY PARALLEL

// Trace Property

TRACE PROPERTY mn l l 0
TRACE PROPERTY mn w w 0
TRACE PROPERTY mp(p) l l 0
TRACE PROPERTY mp(p) w w 0
TRACE PROPERTY mn(n_5v) l l 0
TRACE PROPERTY mn(n_5v) w w 0
TRACE PROPERTY mp(p_5v) l l 0
TRACE PROPERTY mp(p_5v) w w 0
TRACE PROPERTY mn(nds_hviso_320_ehv320) l l 0
TRACE PROPERTY mn(nds_hviso_320_ehv320) w w 0
TRACE PROPERTY ldd(hh) l l 0
TRACE PROPERTY ldd(hh) w w 0
TRACE PROPERTY lddn(nd_hviso_160a_ehv160aus) l l 0
TRACE PROPERTY lddn(nd_hviso_160a_ehv160aus) w w 0
TRACE PROPERTY mn(nds_hv_320_ehv320) l l 0
TRACE PROPERTY mn(nds_hv_320_ehv320) w w 0
TRACE PROPERTY lddn(nd_hv_160a_ehv160aus) l l 0
TRACE PROPERTY lddn(nd_hv_160a_ehv160aus) w w 0
TRACE PROPERTY mp(pds_hv_320_ehv320) l l 0
TRACE PROPERTY mp(pds_hv_320_ehv320) w w 0
TRACE PROPERTY lddp(pd_hv_160a_ehv160aus) l l 0
TRACE PROPERTY lddp(pd_hv_160a_ehv160aus) w w 0
TRACE PROPERTY mn(n_pg400_g2) l l 0
TRACE PROPERTY mn(n_pg400_g2) w w 0
TRACE PROPERTY mn(n_pd400_g2) l l 0
TRACE PROPERTY mn(n_pd400_g2) w w 0
TRACE PROPERTY mp(p_l400_g2) l l 0
TRACE PROPERTY mp(p_l400_g2) w w 0
TRACE PROPERTY rsnd_ehv320 w w 0
TRACE PROPERTY rsnd_ehv320 l l 0
TRACE PROPERTY rsnd_ehv320 r r 0
TRACE PROPERTY rspd_ehv320 r r 0
TRACE PROPERTY rspd_ehv320 w w 0
TRACE PROPERTY rspd_ehv320 l l 0
TRACE PROPERTY rsnpo_ehv320 r r 0
TRACE PROPERTY rsnpo_ehv320 w w 0
TRACE PROPERTY rsnpo_ehv320 l l 0
TRACE PROPERTY rsppo_ehv320 r r 0
TRACE PROPERTY rsppo_ehv320 w w 0
TRACE PROPERTY rsppo_ehv320 l l 0
TRACE PROPERTY rnnd_ehv320 r r 0
TRACE PROPERTY rnnd_ehv320 w w 0
TRACE PROPERTY rnnd_ehv320 l l 0
TRACE PROPERTY rnpd_ehv320 r r 0
TRACE PROPERTY rnpd_ehv320 w w 0
TRACE PROPERTY rnpd_ehv320 l l 0
TRACE PROPERTY rnnpo_ehv320 w w 0
TRACE PROPERTY rnnpo_ehv320 l l 0
TRACE PROPERTY rnnpo_ehv320 r r 0
TRACE PROPERTY rnppo_ehv320 w w 0
TRACE PROPERTY rnppo_ehv320 l l 0
TRACE PROPERTY rnppo_ehv320 r r 0
TRACE PROPERTY rnhrpo_ehv320 w w 0
TRACE PROPERTY rnhrpo_ehv320 l l 0
TRACE PROPERTY rnhrpo_ehv320 r r 0
TRACE PROPERTY d(dion_ehv320) a a 0
TRACE PROPERTY d(dion_ehv320) p p 0
TRACE PROPERTY d(diop_ehv320) a a 0
TRACE PROPERTY d(diop_ehv320) p p 0
TRACE PROPERTY q(pnp_l50x50_ehv320) a a 0
TRACE PROPERTY q(pnp_l100x100_ehv320) a a 0
TRACE PROPERTY q(pnp_l200x200_ehv320) a a 0
TRACE PROPERTY mimcaps_ehv w w 0
TRACE PROPERTY mimcaps_ehv l l 0
TRACE PROPERTY mimcaps_ehv c c 0


**************************************************************************************************************
SUMMARY
**************************************************************************************************************

Total CPU Time: 0 sec
Total Elapsed Time: 0 sec

 

[erikl]

calibre lvs filter unused bipolar

Extraction done? Path to extracted layout correct?

 

[prashantbabu]

lvs reduction priority series

Is this the batch mode Calibre you are using for LVS?
If yes, have you streamed out the gds and updated your rule file with the correct gds path?

 

[Magus]

calibre lvs ignore instance name

It could be that you aren't streaming out the layers correctly, so there could be a mismatch in how it's seeing your layout.

also, do you have the correct rule file(s) for the layout?

what layout tool are you using for your design?