Need help in designing all digital pll (adpll)

[jubin007]

I am designing an ADPLL but am not getting which phase detector to use.
EXOR gate phase detector
JK Flip-flop phase detector
Digital phase frequency detector
DETDFF
moreover there remains a TDC along with it , but some papers tell that TDC alone is sufficient.
please help me understand what should be the preferred choice.

 

[FvM]

PD selection depends on many parameters, e.g. kind of VCO and reference input signals, can be either a bit or word signal, also intended pull and lock frequency range.

 

[jubin007]

i am using all digital pll, so am using NCO. now i have designed two types of NCO, one using LUT and other using cordic algorithm which is controlled by a digital word(14 bit). This is why i need an ADPLL which will analyze and compare these two types of NCO. So i have selected an architecture. 1. phase freq detector (having 2 D-ff having high inputs and reference and feedback in the clocks with outputs as up and down), 2. a control logic which will clock and select up/down 3. an up-down counter- of 14 bit length which will be incremented or decremented by up/down signal and the output is the FSW which will drive the NCO. now I need to know two things.
1. whether this architecture is okay for my application.
2. i don't have any idea how to find lock in range(frequency), lock-in time and other parameters. please help me how to find this.