vidyaredy
Member level 2
dcm_sp
Hi friends,
This is vidya, I am designing a clock doubler(frequency multiplier) using DCM LOGIC in VHDL. I am finding difficulty in using lang constructs. In which i need to multiply the input clock by 2 when (input clock'event and feedback clock'event)='1'. Plz do the needful if u have idea about how ti implement the logic.....Loads of Thanks in advance...
regards,
vidya
Hi friends,
This is vidya, I am designing a clock doubler(frequency multiplier) using DCM LOGIC in VHDL. I am finding difficulty in using lang constructs. In which i need to multiply the input clock by 2 when (input clock'event and feedback clock'event)='1'. Plz do the needful if u have idea about how ti implement the logic.....Loads of Thanks in advance...
regards,
vidya