Need code for generating clock doubler using DCM...

[echo47]

dcm vhdl multiply clock

Yes, you can instantiate Xilinx primitives (such as DCM and BUFG) in your top module. You don't have to put them into separate modules. Also, you don't have to use the Architecture Wizard to generate those clocking modules. I sometimes create an entire project using one big top module and no lower level modules.

You probably already understand this, but just to be sure ---
The Xilinx simulation libraries are not required for synthesis. They are only for simulation. Without the simulation libraries, your simulator doesn't know how a DCM works (or any other Xilinx primitive). The simulation libraries are a collection of VHDL or Verilog modules.

"XST cannot infer a DCM, it must be instantiated." That means XST cannot translate VHDL or Verilog clock-multiplying code (such as delay statements) into a DCM, so the DCM must be instantiated. In my very first message, I didn't know which method you were trying to use.

XST doesn't support any HDL delay statements. I think XST simply ignores delay statements and emits a warning message. I don't know of any synthesis tool that supports HDL delay statements.

Yes I have used different DCM configurations in the same project. My recent "top" module is an example. By coincidence I configured both DCMs as 8-times multipliers, but you could change them by simply modifying the CLKFX_MULTIPLY and CLKFX_DIVIDE parameters. (Beware that some ratios generate more jitter than other ratios.)

 

[vidyaredy]

vhdl dcm multiply frequency

Hi,

I am not using delay elements in DCM, I have used them in the other code. I didn't get clear idea whether can I generate two DCM's under one project with ISE. As u told u write DCM's in VERILOG, I tried in a similar way using VHDL, I have not used delay elements in it.

 

[echo47]

virtex 5 dcm vhdl code

My example has two DCMs, and it synthesizes and routes successfully in ISE. VHDL will also work fine, but I don't know VHDL well enough to write it.

I haven't reproduced the error that's preventing you from using two DCMs, so my best recommendation is to stop using Architecture Wizard or core generator or whichever tool is giving the error message.

 

[vidyaredy]

two dcm ise

Hi,

What is the system clock frequency of SPARTAN 3 FPGA? Is it same as DCM frequency? My entire design works with sytem clock frequency. And I need to generate some ouput pulses for that I am using counter. I need system clock frequncy for that....

 

[echo47]

vhdl dcm

"System clock" usually refers to an external clock signal on your PCB. It clocks multiple devices so they can communicate synchronously. When you design the whole system, You decide which device generates the clock, and you choose an appropriate frequency.

 

[vidyaredy]

dcm_sp_inst verilog howto

Hi,

I need one help. As DCM got constrainted range of freq. beyond or below that it wil not support. Actually my input to DCM is from external world is of very low freq and output of dcm is my clock to ADC even which is very low. Is there any other way to sysnthesize clock i mean multiply clock without DCM'S..............

 

[echo47]

vhdl dcm_sp feedback

The Spartan-3 family provides only DCM for multiplying clock frequency.

Maybe you could use an external PLL synthesizer chip. Here are some from Analog Devices, but I don't know if any of them accept such a low input frequency as 5 MHz. Some other companies make similar devices.
https://www.analog.com/en/rfif-components/pll-synthesizersvcos/products/index.html

 

[vidyaredy]

defparam dcm_inst.dfs_frequency_mode

Even 5 MHZ is too high for my design. Input and output frequency of my entire design is in kilo HZ.

 

[echo47]

dcm jitter clkfx

But earlier you said you had 5 MHz input and needed 320 MHz output.

 

[vidyaredy]

xilinx dcm driving dcm

yeah but I thought I will increase my input frequency and scale down it. Its not happening. Let me discuss with my prof about it. Is there any other device which multiplies clocks of koli hertz?

 

[echo47]

xilinx sram dcm vhdl

National's classic LM565 is a low frequency PLL, although it's now obsolete. I'm not sure which device has replaced it. Maybe the LMC568.
**broken link removed**

A low frequency PLL can also be implemented digitally. That requires a stable high frequency clock for the signal processor.

In the FPGA world, low frequencies are usually generated by simply dividing down a high frequency clock.

I still don't understand what you are attempting to build. You seem to be going in many different directions searching for a solution to something.

 

[vidyaredy]

how to configure a dcm in verilog

yeah u r rite, I am really going around to find solution. Actually I am a fresher in the field dont know how things can be cooked up. I am designing Data Acquisition System. My input is analog signal which is of very low frequency, which is given as input to zero crossing detector(ZCD). As ZCD's output is very low, I am not able to proceed with DCM'S bcz ZCD'S output is my input to DCM. I need two DCMS, bcz I am tapping output of first DCM to generate control signals for my ADC. And output of second DCM will be my input clock of ADC.As ADC CLK is very low acc to datasheets of ADC0808 I need to generate low clock frequency from DCM. I am totally messed up with this.

 

[echo47]

dcm mode in xilinx fpga

Also remember that a DCM input signal must be clean and stable, such as from a crystal oscillator. If the DCM input signal stops and starts, or varies in frequency, or has noise bursts, you must reset the DCM so that it can reacquire lock.

Do you really need the ADC clock frequency to track the input signal frequency? Most data acquisition systems use a stable free-running clock.

The ADC0808 datasheet says the clock must be 10 kHz to 1280 kHz. To generate that clock, I suggest starting with an ordinary crystal oscillator such as 50 MHz, and then build a simple counter (not a DCM) in the FPGA to divide the 50 MHz down to your desired ADC clock frequency.

What happened to the 320 MHz ADC clock? Did you mean 320 kHz?

 

[vidyaredy]

dcm example

okay....Thank u very much. Even I was thinking to divide clock frequency.If I do that I can get ADC-CLK. But I need to rule out the use of ZCD, and I wil be giving the input directly ADC.....?

 

[echo47]

cascading dcms

Your last few words are unclear, sorry. I don't know enough about you project to understand why you considered using the ZCD clocking scheme. Maybe you had an important reason for doing that. Or maybe not.

 

[vidyaredy]

vhdl dcm wizard

I am giving my analog input to ZCD and with the help of clock synthesizers I am generating clock to ADC and I am generating control signals for ADC.i.e., SHG(Sample and hold),SOC(start of conversion) with logic gates. I Hope you got my point....

Added after 2 minutes:

One more doubt where do I find the dutycycle for ADC CLOCK of ADC0808?

 

[echo47]

dcm2x verilog example

Maybe you have a special reason for clocking the ADC that way. Seems strange though. Most applications need a clean stable ADC clock such as from a crystal oscillator.

I don't see any duty cycle spec in the ADC0808 datasheet. I suggest either asking National, or try using a square wave.

 

[vidyaredy]

bufg clk2x_bufg_inst verilog

Hi,

How do I find out delay for buffer primitive in spartan 3.

 

[mahankalisatish]

dcm vhdl

this is the code generated from Core generator ..for vertex 4 family for which the freuency range is 32 to 150 Mhz i have given minimum freq 32 Mhz.

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity DCM_Clkx2 is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM_Clkx2;

architecture BEHAVIORAL of DCM_Clkx2 is
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
signal GND_BUS_7 : std_logic_vector (6 downto 0);
signal GND_BUS_16 : std_logic_vector (15 downto 0);
begin
GND_BIT <= '0';
GND_BUS_7(6 downto 0) <= "0000000";
GND_BUS_16(15 downto 0) <= "0000000000000000";
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);

CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLK0_OUT);

DCM_ADV_INST : DCM_ADV
generic map( CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>GND_BIT,
CLKIN=>CLKIN_IBUFG,
DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
DCLK=>GND_BIT,
DEN=>GND_BIT,
DI(15 downto 0)=>GND_BUS_16(15 downto 0),
DWE=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>open,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
DO=>open,
DRDY=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open);

end BEHAVIORAL;


I have not tested the code but I have generated the for my work where the I need multiplied bty 6 clk...

 

[vidyaredy]

dcm_sp vhdl

Thank u very much but my interest is to work with very low frequencies of khz. I cant use DCM'S as it operates only with frequencies of Mhz.