Need code for generating clock doubler using DCM...

[vidyaredy]

dcm_sp

Hi friends,

This is vidya, I am designing a clock doubler(frequency multiplier) using DCM LOGIC in VHDL. I am finding difficulty in using lang constructs. In which i need to multiply the input clock by 2 when (input clock'event and feedback clock'event)='1'. Plz do the needful if u have idea about how ti implement the logic.....Loads of Thanks in advance...

regards,
vidya

 

[echo47]

clock generation without dcm

If you are trying to infer a DCM by writing behavioral HDL, well, the Xilinx tools don't support that. You need to instantiate the DCM primitive into your HDL. DCM instantiation syntax is described in the Libraries Guide for your particular FPGA. If you need to understand how the DCM operates, see your FPGA user guide and/or data sheet.

 

[vidyaredy]

clock doubler verilog

Hi,

Thank u very much for quick response. I have gone thro'the manual acc to it, it wil generate lock out signal='1' and dll output clk2x=2*f(clk_in)....when (clk_'event and clk_fb'event)='1'. Its not supporting this format. And Xilinx ISE will generate dcm instance using architecture wizard but no logic behind and at the end i can only use the instance of that. However I need to write the code for lower level dll.....I can generate frequency multiplication or clock doubler using gates but i need to do with DCM....Plz let me know if u have any idea.

 

[echo47]

xilinx dcm vhdl

I can't quite understand your second message, sorry.

I don't know VHDL very well, but maybe this Verilog example will help you. It inputs a 50 MHz clock, doubles it to 100 MHz, and then clocks a simple counter. It synthesizes into a Spartan-3, a Virtex-5, and maybe other FPGA types too.

module top (clk50, count);
  input             clk50;      // synthesis attribute period clk "50 MHz";
  wire              clk50dcm, clk100dcm, clk100;
  output reg  [7:0] count = 0;

  DCM dcm100 (.CLKIN(clk50), .RST(1'b0), .CLKFB(clk50dcm), .CLK0(clk50dcm), .CLK2X(clk100dcm));
  defparam dcm100.CLKIN_PERIOD = 20.0;
  BUFG buf100 (.I(clk100dcm), .O(clk100));

  always @ (posedge clk100) begin
    count <= count + 1;
  end
endmodule

That's only an example. The DCM is highly configurable, so be sure to read the user guide and data sheet for your FPGA, and use whichever DCM connections and parameters are appropriate for your project. Some folks prefer to use the wizard instead because it hides many of those details.

 

[vidyaredy]

dcm instantiation

Hi,

The one which u have sent is it the instance for dcm? could u plz explain the main logic, I tried to simulate ur code in ise 8.1 but i failed to get multiplied frequency output.

 

[echo47]

clock doubler

Yes, my example shows Xilinx DCM instantiation. The DCM simply inputs 50 MHz and outputs 100 MHz. The BUFG is a global clock buffer, necessary for driving the clock net.

I'm using ISE 10.1.01. Here's the display in ModelSim 6.3g. What does your simulation look like? Or did you get error messages?

 

[vidyaredy]

spartan-3 dcm does not lock

Hi,

I am using ISE 8.1I and modelsim 6.1b. I have verified with ISE simulator where I am getting output in z (high impedence state)state and rest all in zero. Do I need to add some more logic into the code u have sent r directly run in s/w? Thank u very much for giving me clues.

Added after 11 minutes:

Hi,

do I need to add lower level modules as BUFFER, COUNTER...and one more query in ur code u have mentioned DCM instance then do I need to code for dcm. I am in hurry and just run ur code in s/w to verify the output. Bit Confused.

 

[MagixD]

dcm code example

Hello,

This is the VHDL code to instance a DCM

 DCM_SP_inst : DCM
   generic map (
     CLKFX_DIVIDE          => 5,
     CLKFX_MULTIPLY        => 8,
     CLKIN_DIVIDE_BY_2     => FALSE,
     CLKOUT_PHASE_SHIFT    => "NONE",
     CLK_FEEDBACK          => "NONE",
     DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS",
     DFS_FREQUENCY_MODE    => "LOW",
     DUTY_CYCLE_CORRECTION => TRUE,
     FACTORY_JF            => X"8080",
     PHASE_SHIFT           => 0,
     STARTUP_WAIT          => FALSE)
   port map (
     CLK0	 	=> open,
     CLK180 	=> open,
     CLK270 	=> open,
     CLK2X	=> open,
     CLK2X180	=> open,
     CLK90 	=> open,
     CLKDV 	=> open,
     CLKFX 	=> open,
     CLKFX180   => open,
     LOCKED 	=> open,
     PSDONE 	=> open,
     STATUS 	=> open,
     CLKFB 	=> open,
     CLKIN 	=> open,
     PSCLK 	=> open,
     PSEN 	=> open,
     PSINCDEC   => open,
     RST 		=> open
   );

For an description of the signals, use any Xilinx FPGA datasheet (for example Spartan-3 full datasheet, page 29).
If you connect CLKIN with your input clock, the DCM will output the double frequency on CLK2X.

magixD

 

[vidyaredy]

dcm2x.v

Hi...

This is the code for instantiating in top module rite...

 

[echo47]

xilinx dcm to dcm

My example is ready to synthesize into an FPGA, although it doesn't constrain pin numbers. To simulate it, you must of course provide a testbench that generates the 50 MHz input clock.

"output in z" - do you mean the counter output is floating? That doesn't make sense, it's a register initialized to zero. Maybe you have disconnected signals somewhere.

If your simulation shows all the other signals are zero, I guess you mean the input clock is also zero. If that's true, then you need to debug your testbench clock generator.

Can you show us your code and simulation output? It's difficult to guess what's wrong without seeing any evidence.

 

[echo47]

xilinx dcm verilog example

Which FPGA are you using? How many MHz are you generating? Be sure you don't violate the DCM's maximum output frequency or minimum input frequency.

Xilinx says don't cascade more then two DCMs due to jitter accumulation. Besides, six doublers would give you 64 times frequency, not 12 times frequency. Also, to multiply a clock by 6 or 12, you can use one DCM (the CLKFX output).

DCM jitter (hundreds of picoseconds) will add noise to your ADC signal acquisition. If that's a concern for your project, then you should use a high-frequency input clock and eliminate the DCMs.

I don't understand "what are the basic blocks do I require to use DCM from ISE". What do you mean by "block"? ISE doesn't require any preparation before using a DCM.

 

[vidyaredy]

xilinx cascading dcm_sp

I am using spartan 3, and min frequency for it is 18MHZ. U have sent the simulated output for dcm rite with 50MHZ input freq and output freq of 100MHZ. Then later u said i need to generate a clock of 50 MHZ using testbench. In the dcm instance they have mentioned BUFG,IBUFG,DCM instances. If u dont mind could u plz send me the all files that u have used to generate 100 MHZ from 50 MHZ...and steps in the order which I have to fallow.....I would like see outputs and verify how actually it works and then I wil decide how I should go further. sorry that I did a mistake in plotting no. of multipliers. What i meant is first pll or dll consists of N=6 and later one with N=12(For first i used 3 dcms with each dcm n=2 clock doubler).

 

[echo47]

modelsim xilinx dcm

I have no more files.
My testbench won't help you -- it won't work with ISE Simulator.
I don't know how to use ISE Simulator, sorry. It probably provide some easy way to generate a clock.

Your words are unclear -- what input and output frequencies do you need?

 

[vidyaredy]

dcm double clock xilinx manual

Hi,

I have written a code to generate freq doubler its working fine with vhdl but not in verilog. My software is generating only verilog DCM instances. I have attached my files of DCM, DCM instance, clock doubler and top module. Could u plz check the clock doubler code let me know where I have gone wrong....?

 

[echo47]

xilinx dcm port

I think you are having difficulty writing a Verilog testbench. Your clk50 module contains syntax errors (it won't compile), integer division that gives zero result, and it never instantiates the module to be tested.

Try this. I added a simple testbench module that generates a 50 MHz clock:

// synthesis translate_off

`timescale 1 ns / 1 ps

module testbench;
  reg clock = 1;
  always #10 clock <= ~clock;     // 50 MHz clock
  top top (.clk50(clock));        // instantiate the top module
endmodule

// synthesis translate_on


module top (clk50, count);
  input             clk50;      // synthesis attribute period clk "50 MHz";
  wire              clk50dcm, clk100dcm, clk100;
  output reg  [7:0] count = 0;

  DCM dcm100 (.CLKIN(clk50), .RST(1'b0), .CLKFB(clk50dcm), .CLK0(clk50dcm), .CLK2X(clk100dcm));
  defparam dcm100.CLKIN_PERIOD = 20.0;
  BUFG buf100 (.I(clk100dcm), .O(clk100));

  always @ (posedge clk100) begin
    count <= count + 1;
  end
endmodule

 

[vidyaredy]

dcm in vhdl

Hi,

I tried with ur testbench for clock its working fine. Now the issue is when I simulated the DCM module I got the error as,

E:/TRY/DCM.v(50): Instantiation of 'DCM' failed. The design unit was not found.
# Region: /dcm2x,.

Do I need to write a code for DCM_INST, again the question raised to me was logic for that, I just did the input assignments to output and named it as DCM_INST.

At the end when I simulated the DCM module I got the erros as..

E:/TRY/DCM.v(51): Unresolved reference to 'CLK_FEEDBACK' in DCM_INST.CLK_FEEDBACK.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(54): Unresolved reference to 'CLKFX_MULTIPLY' in DCM_INST.CLKFX_MULTIPLY.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(56): Unresolved reference to 'CLKIN_PERIOD' in DCM_INST.CLKIN_PERIOD.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(58): Unresolved reference to 'DESKEW_ADJUST' in DCM_INST.DESKEW_ADJUST.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(59): Unresolved reference to 'DFS_FREQUENCY_MODE' in DCM_INST.DFS_FREQUENCY_MODE.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(60): Unresolved reference to 'DLL_FREQUENCY_MODE' in DCM_INST.DLL_FREQUENCY_MODE.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(61): Unresolved reference to 'DUTY_CYCLE_CORRECTION' in DCM_INST.DUTY_CYCLE_CORRECTION.
# Region: /dcm2x
# ** Error: (vsim-3043) E:/TRY/DCM.v(62): Unresolved reference to 'FACTORY_JF' in DCM_INST.FACTORY_JF.
# Region: /dcm2x
# Error loading design


Sorry the images are too big I 'm not able to attach with this mail, that why I have copied the text msg...

 

[echo47]

modelsim warning vsim-3473 clock

I'm not clear which code you are trying to simulate. If my 24-Jun-2008 example is working fine, then which code is causing all those error messages?

To avoid confusion, upload your HDL files in a ZIP or RAR archive. Don't use a Word document.

 

[vidyaredy]

vsim-3473

Please find the attached zip file. which consists of codes for clock generator with 50MHZ freq, DCM,buf, ibuf, top module. When I simulate DCM and top module I am getting error as DCM instance not found.
Please let me know where I am going wrong....

 

[echo47]

how to double the frequency using dcm in vhdl

You shouldn't need to create any modules for Xilinx primitives like BUFG or IBUFG. Maybe you haven't finished installing your simulator. See section "Compiling the Xilinx Simulation Libraries" in your ISE "Synthesis and Simulation Design Guide". That step is essential for simulation, unless you are using the special Xilinx version of ModelSim that includes pre-compiled simulation libraries. That would also explain "DCM not found".

 

[vidyaredy]

dcm_sp dcm jitter

Hi,

I have simulated these files in modelsim 6.1b. when I simulated in ISE simulator 8.1i , OUTPUT was in z state....Sorry I am not finding the section Compiling the Xilinx Simulation Libraries in Xilinx Synthesis and Simulation Design Guide. I am using Xilinx ISE 8.1i. Is it possible for u to make some alterration in my code and revert me back. will be great help....