Need Clarification On Current Mode Logic (CML) Specification

[suria3]

common mode logic

Dear People,

Currently i'm doing research on CML Design. From what i have found so far, there were no fixed common mode voltage or signal swing for both CML driver and receiver. From the collected datasheets from many companies, what can I see is there are some range but not a fixed one. For example :-


1) Maxim
- CML Driver Differential Output Swing ( 640mVpp - 1000mVpp)
- CML Receiver Differential Input Swing (400mVpp - 1200mVpp)

2) Other companies
- CML Driver Differential Output Swing (400mVpp - 1300Vpp)
- CML Receiver Differentilal Input Swing (400mVpp - 1600mVpp)


So, can anyone clarify for me what is the actual swing range needed by both the CML Driver and Receiver and the DC Common mode as well like LVDS have 1.2V CM with 800mVpp differentially.
Is there any standard i need to follow on.

Now let say, my typical design is 800mVpp differentially, is that mean that for any temp & process variation , my signal swing must be exactly 800mVpp or it can change within the range??


Thanks in advance,
Suria3

 

[krashkealoha]

cml spec

I haven't seen any "standard" voltage levels for CML outputs. Since many of the applications are at high speed, the parts are driven differentially vs. single-ended. Therefore, having a specific VOH or VOL level is not required, like how it was in say ECL.

The size of the output swing is dependent on the application. In more receiver applications, the emphasis is on being able receive a small input voltage thus the output voltages are usually on the order of 800 mVpp-differential. When used as a driver, for example in a backplane, attenuation of the output voltage occurs driving a long copper line therefore a larger output swing is required. Some of the drivers are also used to drive a VCSEL so their output swing is dependent of the VCSEL's characteristics for lasing.

In terms of common mode range, bigger the better because that allows your part to be interfaced with a larger variety of interfaces, eg. CML, PECL, RSPECL, LVDS, CMOS etc.. In the end you will be limited by your supply voltage, bandwidth and the circuit topology chosen for your input stage.

Per your design of 800mVpp-differential output, you should target that as your typical output swing. There should also be a min. and max. output swing targets. If the output swing is too large, then more power is consumed if your part is interfaced with a part with input termination to the top voltage supply. If your output swing is too small, then the receiving part may not have the input sensitivity to amplify your signal.

You should try to keep your output peak to peak voltage constant at a target, min./max, output voltage over your frequency range for variations in temp., voltage supply, and process variations. Once your output peak to peak voltage starts to attenuate at a certain frequency, that determines the bandwidth of your part. In addition, for receiving applications you might want to keep the gain of the part constant over temperature so it can be used in some applications as an amplifier. Furthermore, keeping gain changes minimal over temperature will allow a better bandwidth at hot temperature, where the gain usually falls off thus causing your bandwidth and input sensitivity to degrade too.

I hope this helps. I just glossed over the major points because each application has its own sets of optimization criteria.

 

[surianova]

current mode logic specification

I olso design the CML driver now. Just have one question. Is it the output swing of driver must be constant , let say 800mV diffrentially peak to peak. Because from my simulation it vary from 800 mv to 1100 mv across process and temperature. Is it aceptable?

 

[suria3]

cml current mode logic

Hi krashkealoha,

Thanks for the information. As per now, the CML which i have designed have the Differential voltage at 800mVpp at Typical Process and 27 deg. But when i run over other process & temperature the swing vary from 640mVpp - 1100mVpp differentially. And the CM at typical is 1.5V and this vary from 1.465V to 1.540V over process & temp. So, is this design can be accepted as the CML driver.

Another question is my CML driver gain is showing -7dB, which i guess is a attenuation coz my input signal to CML is 400mVpp with CM of 1.2V. So, in this how do i measure the gain and bandwidth of the CML. As you said, when output of CML start to attenuate at certain frequency, that is the bandwidth of the part,but for my case i couldn't see any attenuation coz all the signal have good output waveform. Hope can give more clear picture on this matter.

Bye,
Suria3

 

[alanbrooke]

cml specification

Dear All,
I just begin to study the CML driver and receiver, I have checked a lot of CML products datasheet, but I am very curious that there is no such spec for the loading capacitance for the driver, only several resistors and transition line. If I set the Cload=10pF, the rise and fall time can not meet the spec.
I also can not make sure the common mode voltage range for the CML receiver.
Can you help me these questions, Thank you very much!

 

[krashkealoha]

cml driver

Suria,

Your Vout_pp voltages are ok, but if you can reduce the spread, I would try to improve it. Find out what condition is giving your the greatest variation. For example, if you Vout_pp is varying with temperature, you might look into using a PTAT for biasing. On the other hand your common-mode range is too small. If you are operating off a 1.8V supply, you should at least achieve a 500-800mV common-mode range of operation.

Another question is my CML driver gain is showing -7dB, which i guess is a attenuation coz my input signal to CML is 400mVpp with CM of 1.2V. So, in this how do i measure the gain and bandwidth of the CML. As you said, when output of CML start to attenuate at certain frequency, that is the bandwidth of the part,but for my case i couldn't see any attenuation coz all the signal have good output waveform.

To measure the gain bandwidth you need to either run an AC simulation or measure S21 in a s-parameter simulation. The driver needs to be operating in small-signal mode to achieve a proper gain and upper 3dB value. To get a large-signal bandwidth under your condition, you can force a 400mVpp signal over a frequency range of interest. You then measure the output peak to peak voltage and plot a Vout_pp vs. Frequency for a 400mVpp input. This will give you an idea how your part will operate over frequency with a 400mVpp input. Looking at the quality of the waveform is also important because this translates to duty cycle distortion or pulse width distortion.

In response to alanbrooke:
If you need to drive 10pF, your bandwidth will not be high as you stated. The load is all dependent on the application. Find out how they are going to use this part in a system. For example, if you are driving a laser, then your load capacitance will be the capacitance due to the package you are using, capacitance associated with the microstrip line, plus the capacitance of the laser diode. I haven't seen a standard load for a CML output.

 

[johnlzy]

Re: Need Clarification On Current Mode Logic (CML) Specifica

Hi everyone,

I am rather new to differential pair signalling and I have a simple question.

I am trying to connect a CML SerDes output of a microchip to my laser driver (for fiber optic communication purposes).

The output signals of the microchip are: SOP (serial output positive) and SON (serial output negative).

At the Laser driver they are: DIP (driver input positive) and DIN (driver input negative).

Logically, I will connect SOP to DIP and SON to DIN (i.e. positive to positive and negative to negative).

However, in doing so, my differential traces needs to travel in a round about fashion due to the nature of the connector and this introduces additional unwanted transmission line reflections.

To solve this, I am thinking of connecting SOP to IN and SON to IP (i.e. negative to positive and vice versa). Might this be even possible? My rationale is that this would work because they are differential signals.

Cheers!
John

 

[JoannesPaulus]

If you do not care about the phase, it will surely work but notice that when you send a 0 you will receive a 1 and vice versa.