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entity my_design is
Port( clk : in std_logic;
input : in std_logic;
output : out std_logic);
end my_design;
architecture Behavioral of my_design is
signal input_old: std_logic;
begin
process(clk)
begin
if(clk'event and clk='1') then
if(input_old /= input) then
output<='1';
else
output<='0';
end if;
input_old <= input;
end if;
end process;
end Behavioral;