library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity signed_integ is
generic
(
DATA_WIDTH : natural := 8
);
port
(
clk : in std_logic;
reset : in std_logic;
a : in signed ((DATA_WIDTH-1) downto 0);
result : buffer signed ((DATA_WIDTH-1) downto 0)
);
end entity;
architecture rtl of signed_integ is
begin
process (clk,reset)
begin
if reset = '1' then
result <= (others => '0');
elsif rising_edge(clk) then
result <= result + a;
end if;
end process;
end rtl;