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need a simple source code

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farrokhiyan

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Hi all,
I'm a beginner in vhdl. i need a simple source code for digital integrator in vhdl which is synthesizable on FPGA. can you help me?

tnx.
 

FvM

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Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity signed_integ is
  generic
  (
    DATA_WIDTH : natural := 8
  );
  port 
  (
    clk    : in std_logic;
    reset : in std_logic;
    a       :  in signed	((DATA_WIDTH-1) downto 0);
    result : buffer signed ((DATA_WIDTH-1) downto 0)
  );
end entity;

architecture rtl of signed_integ is
begin
  process (clk,reset)
  begin
    if reset = '1' then
      result <= (others => '0');
    elsif rising_edge(clk) then	
      result <= result + a;
    end if;	
  end process;
end rtl;
 

    farrokhiyan

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