my flip-flop does not change state between 1.2 V and 0 V

mohamis288

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Hello,

I have created a flip-flop using the following structure:



it is my flip-flop testbench circuit:


I have simulated this circuit and here is output result:




it seems it wants to change, but it can not. what is the problem do you think?

I have tested Nand3 lonely in schematic and it works correctly. here is the testbench for simulation of NAND3 and output result of NAND3:


 

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That is a latch (at best, if wired right). A flip-flop has master and
slave latches.

Crack open any '80s RCA CMOS databook and find schematics.
 

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Here is the link to this flip flop:

VHDL Tutorial 17: Design a JK flip-flop (with preset and clear) using VHDL

Note: it’s recommended to follow this VHDL tutorial series in order, starting with the first tutorial. In the previous tutorial – VHDL tutorial 16 – we designed a D flip-flop circuit by using VHDL. For this project, we will: Write a VHDL program to build a JK flip-flop circuit Verify the output...
www.engineersgarage.com

I just used this
 

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Then this is a lesson about believing things you find on the Internet.
As is far too common "the exercise is left..."

Begin with some reading on latches / half-latches / flip-flops and the
classic forms (these days nobody makes D FFs out of NAND gates
and hardly anyone uses a JK unless they are doing custom transistor
level, primitive gate level bottom-up).
 

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