[MOVED] question regards to basic logical gates

[DE4User]

Hi guys,

Suppose the propagation delay for a AND gate with two inputs is 20ps. How about the propagation delay for a AND gate with three inputs or four inputs under the same fabrication technique? Thanks.

 

[amu_cpln]

Re: question regards to basic logical gates

prorogation delay characteristics of gates vary between different manufacturers .. maybe based on fabrication techniques used
so .. for a new fabrication ... an altogether different part .. the delay depends on the technique used
yet .. for your example ,, it is possible to fabricate ic's with same delay
though your delay is really good (very low)

 

[DE4User]

Re: question regards to basic logical gates

Thank you so much. But I have one more question, do you know the propagation delay for AND2, OR2, NOT and D flip-flop based on the popular fabrication technique? Thanks.

 

[amu_cpln]

Re: question regards to basic logical gates

depending on gate and manufacturer .. usually varies from 1 ns to 10 ns
is also a function of voltage .. lower delay at higher voltage

 

[DE4User]

Re: question regards to basic logical gates

Someone told me the following, is that true?
propagation delay of the 65nm lpsvt process:
1. propagation delay for AND2 is from 25 to 40ps.
2. propagation delay for OR2 is from 25 to 45ps.
3. propagation delay for NOT is 10ps.
4. propagation delay for D flip-flop is 60ps.

 

[amu_cpln]

Re: question regards to basic logical gates

i did not come across gates with such less delay..though i am aware of the technology you mention ..
There are IC's fabricated using 25nm too, but new technology comes at its price
and i have not come across a commercial ic's having such low delay

 

[keith1200rs]

Re: question regards to basic logical gates

You need to be clear if you are talking about the propagation delays of gates within an IC or the delay of a packed IC with input and output circuitry and ESD protection - the values will be totally different.

Keith

 

[DE4User]

Re: question regards to basic logical gates

I am talking about the propagation delays of gates within an IC, so do you know the delay for AND2, OR2, NOT and D flip-flop based on the popular fabrication technique? and suppose the delay for an AND2 gate is unit 1, what about the delay for AND3 or AND4 under the same fabrication? Thanks.

---------- Post added at 18:11 ---------- Previous post was at 18:10 ----------

I am talking about the propagation delays of gates within an IC, so do you know the delay for AND2, OR2, NOT and D flip-flop based on the popular fabrication
technique? and suppose the delay for an AND2 gate is unit 1, what about the delay for AND3 or AND4 under the same fabrication? Thanks.

 

[keith1200rs]

Re: question regards to basic logical gates

Yes, I will have some data for a few processes but cannot access it until I am work again on Monday. The figures posted here edaboard.com/thread249359.html#post1066731 sound reasonable.

Keith

 

[DE4User]

Re: question regards to basic logical gates

Thank you so much. But I am wondering if the delay for an AND gate with two inputs is 20ps, what about the delay for a four-input AND gate? How many time slower it will be than a two-input AND gate? Thanks.

 

[amu_cpln]

Yes sure .. at gate level .. transistors do need delay in order of ps ..and is a function of operating voltage (lower voltage lesser time)
Here is the transistor equivalent of common logic gates



The NOT gate is simply a transistor interverter .. so adds the delay for one transistor only

These are gates with two inputs only .. but gates with additional inputs can be implemented by adding transistor/inputs in series/parallel
the delay is not same in each case .. in AND gate where all are in series .. the delay adds up ..
while for parallel combination as in OR gate the max delay of single transistor will be the gate delay

fabrication may not use exactly this equivalent, may use mosfets, and may also use universal gates to realize common logic functions
Yet these equivalents can give you a brief idea of the delay timings .. Hope it helps

 

[DE4User]

Thank you so much. I really appreciate it.

 

[keith1200rs]

Examples from a 0.8um process:

AND2 0.25ns
AND3 0.28ns
AND4 0.29ns
AND5 0.33
AND6 0.32
AND7 0.41
AND8 0.32
NOT 0.1ns
OR2 0.34ns
OR3 0.37ns
D type 1.48ns

Keith