[moved] How to code System Verilog AMBA read write tasks

[sai685]

Can any one send me qlues codes regarding
1. Write a task to perform write operation which includes four states such as NON_SEQ,SEQ,IDLE,BUSY. in which NON_SEQ state means it is indicating start of a transfer, and BUSY means not ready to transfer, SEQ means a continuos transferring
2 . In the same way read task

 

[sai685]

Re: Regarding write and read in AMBA architecture

I want it in system verilog
Write separate task for each read and write. (and also for each master/slave)
- I need to drive the htrans signal. (not just sample)
- If I have initiated a transfer. I need to wait for relevant signal to get asserted. (you cannot just check for ready and exit the task, i.e. if master initiated a write transfer then it should wait until slave ready is high, also have a timeout of 20 clock and exit, i.e. exit if slave ready doesn't come within 20 clock).
-Relevant signals in the sense check whether the slave is ready or not and the response of slave which should be done automatically