Mosfet working in sub-threshold region

[AllenD]

Hi guys
I understand there are designs intentionally bias the transistors in the sub-threshold region for higher gm/I.

But what if unintentional? I have a common-drain connected nmos, whose source is connected to a resistor in my IC design. The nmos works in region 3 (in cadence, region 3 means sub-threshold). I think it is because the drain current (Id) is too small for its W/L. So when I annotate the working condition, Vgs is slightly smaller than vth as is defined in sub-threshold. But the Vdsat is POSITIVE (I guess this is normal for sub-threshold region).

My question is that is the simulation reliable given this subthreshold region is un-intentionally achieved. If I tape-out the circuit, will the transistor fall into cutoff instead during measurement since it definitely match with the vgs<vth reguirement?

Thanks
Allen

 

[dick_freebird]

This depends on the quality of the foundry PDK models.
A "digital" flow must be suspect, as this region is not in
the mainstream of applications and would only affect
SPICE simulations of leakage in the context of a digital
library based design.

You would expect an analog / mixed signal kit to pay more
/ better attention to this.

ID "too small" for W/L might mean simply that other things
(noise, matching, voltage drop) matter more than model
accuracy, or accuracy was judged OK.

At any rate if you care about physical outcomes then some
effort to validate model accuracy and coverage of process
variation, is warranted. You may or may not find modeling
docs from the foundry (laying about, or by request) that
speak to the care taken and results achieved.

 

[AllenD]

Hi Sir
Yes, I am using TSMC 65nm rf/mix signal PDK. If I understand you correctly, do you mean this PDK is more accuratly capture the sub-threshold region working?

Can I please ask a follow-up question based on your comment "ID "too small" for W/L might mean simply that other things (noise, matching, voltage drop) matter more than model accuracy or accuracy was judged OK. " Do you mean in such case, the noise/matching etc is worse then the simulation suggested?

Thanks again
Allen

 

[AllenD]

Hi Mr freebird
Just to make my response/question clear, concerning your mentiond 3 specs:

1. I sort of understand what you meant about noise. Did you mean the thermal noise 4KT*gm? When I have a large W/L, the gm is larger so the thermal noise is larger? But I thought for flicker noise k/WLCoxf, bigger W and makes it better.

2. I thought bigger transistors means easier to match. What matching did you mean?

3. I am not so sure about voltage drop. Can you please elaborate? Which chapter of the book talks about this?

Thanks
Allen

 

[dr_kca]

You may try to run SOACHECK if your simulator supports that (assuming TSMC models have their SOAs defined). This can tell at least if the operating modes are accurately modeled.