AllenD
Member level 5
Hi guys
I understand there are designs intentionally bias the transistors in the sub-threshold region for higher gm/I.
But what if unintentional? I have a common-drain connected nmos, whose source is connected to a resistor in my IC design. The nmos works in region 3 (in cadence, region 3 means sub-threshold). I think it is because the drain current (Id) is too small for its W/L. So when I annotate the working condition, Vgs is slightly smaller than vth as is defined in sub-threshold. But the Vdsat is POSITIVE (I guess this is normal for sub-threshold region).
My question is that is the simulation reliable given this subthreshold region is un-intentionally achieved. If I tape-out the circuit, will the transistor fall into cutoff instead during measurement since it definitely match with the vgs<vth reguirement?
Thanks
Allen
I understand there are designs intentionally bias the transistors in the sub-threshold region for higher gm/I.
But what if unintentional? I have a common-drain connected nmos, whose source is connected to a resistor in my IC design. The nmos works in region 3 (in cadence, region 3 means sub-threshold). I think it is because the drain current (Id) is too small for its W/L. So when I annotate the working condition, Vgs is slightly smaller than vth as is defined in sub-threshold. But the Vdsat is POSITIVE (I guess this is normal for sub-threshold region).
My question is that is the simulation reliable given this subthreshold region is un-intentionally achieved. If I tape-out the circuit, will the transistor fall into cutoff instead during measurement since it definitely match with the vgs<vth reguirement?
Thanks
Allen