Monitering or Accessing an Internal Signal at Top Level

[Mirzaaur]

Hi all,

Please advise me about my problem:-

I am simulating top level (VHDL) , need to moniter an internal signal of component. IN my test bench I want to generate the test signal based on the value of that signal what should I do ?

I am using Aldec 7.

One way is to assign a (test) port to that signal and then moniter that port, but it cause a mess in design.

thanks in advance,

mirza

 

[aji_vlsi]

Hi all,

Please advise me about my problem:-

I am simulating top level (VHDL) , need to moniter an internal signal of component. IN my test bench I want to generate the test signal based on the value of that signal what should I do ?

I am using Aldec 7.

One way is to assign a (test) port to that signal and then moniter that port, but it cause a mess in design.

thanks in advance,

mirza

Hi,
You may be aware that VHDL language does NOT allow that per-se. Having said that many simulators allow that via special functions/procedures. Aldec has this feature named "SignalAgent", look for it in their doc. Also take a look at

www.noveldv.com/eda/probe.zip for a generic package that I wrote a while ago for this.

HTH
Ajeetha, CVC