I'm trying to simulate a very small piece of SystemVerilog code with ModelSim 6.0d. It compiles without errors, but when I try to add the signals to the wave, I get this error:
Code:
# (vish-4014) No objects found matching 'sim:/test_iterface_tb_v/*'.
(note: there's a typo, iterface should be interface, but that shouldn't make any difference.)
variables inside a process may not be logged by default. you may need vcom +acc=v and also type "log pmt_if_tb/U_0/p_seq_offset/test_variable" explicitly.
We advise not using the -novopt switch, and it will become an error in the next release of ModesSim/Questa. Use +acc=... (BTW, this is not an issue for the "free" versions of Modelsim because it has no optimizations.