Verilog-XL is too slow for designer to verify a large design. I have done some comparisons between VCS and NC before (using a 400000 gates design). Here is my result:
In RTL simulation, VCS is the fastest. Its simulation time is about 10% faster than NC.
But in gate-level simulation, VCS is about 20% slower than NC, and sometimes it will occur some unrecoverable error (core dump or cause wrong signal value 'X' during simulation) and less robustness.
In my opinion, I think NC is a better choice. Modelsim, as I know, is much slower than both VCS and NC; but it provides good Verilog and VHDL co-simulation. :smile: