Modelsim - can see the gain in perfomance in new versions

[buzkiller]

Hi,

In the past 2 years I have worked with Modelsim SE 5.3 to 5.5a .
All these versions gave me practically the same performance in VHDL.
Every major new version has promised 2-4 times gain in performance.
Why don't I see it? May be it's only for Verilog ? Please share your experience.

P.S. (I tested on PII-450 with 256MB RAM)

Buzkiller.

 

[wzj]

Which HDLSim tool is better(performance), like NC-Sim, VCS, Modelsim ...?

Thanks!

 

[wangjill]

In behavior model, modelsim is the best by myself. In gate level, it is very very very very slow.

By the way, what difference in the NC-verilog and Verilog-XL ??

Who can tell me the answer?

 

[wangjill]

No one to answer me! That's ok!! I will answer me by myself.

After surveying, NC-Verilog is compiled-base Verilog simulator, Verilog-XL is interpret-based. In the speed, NC-Verilog is faster(several order) than Verilog-XL; Particularly in the gate level.

I think that in the behavioral model to use modelsim or NC-Verilog, in the gate model to use NC-Verilog is the best soluation.

Anyone has other comments?

 

[roZes]

<font size=-1>[ This Message was edited by: roZes on 2001-06-27 18:52 ]</font>

 

[liu029]

Verilog-XL is too slow for designer to verify a large design. I have done some comparisons between VCS and NC before (using a 400000 gates design). Here is my result:

In RTL simulation, VCS is the fastest. Its simulation time is about 10% faster than NC.

But in gate-level simulation, VCS is about 20% slower than NC, and sometimes it will occur some unrecoverable error (core dump or cause wrong signal value 'X' during simulation) and less robustness.

In my opinion, I think NC is a better choice. Modelsim, as I know, is much slower than both VCS and NC; but it provides good Verilog and VHDL co-simulation. :smile:

 

[roZes]

<font size=-1>[ This Message was edited by: roZes on 2001-06-27 18:52 ]</font>

 

[liu029]

wow... your design is really so BIG (10M gates or transisotrs?)!

1 gate = 1 smallest 2-input NAND = 2 P + 2 N-type transistors.

What process do you use? .18um?

The versions of NC and VCS I used are: LDV3.0/3.1 and VCS5.IN1. And SDF information is also included during whole-chip gate-level simulation. I use NC not only for its speed but also its stability. :smile:

 

[roZes]

<font size=-1>[ This Message was edited by: roZes on 2001-06-27 18:52 ]</font>

 

[liu029]

mm... I finally realize that why my RTL simulation is so slow now. :smile:

Recently, I use PLI to build models of ADC/DAC/PLL to let verilog could do mixed-mode simulation. However, the speed becomes slow. Your post tell me why... thx, roZes. Maybe I can switch back to VCS to try my further simulations. :smile:

 

[roZes]

<font size=-1>[ This Message was edited by: roZes on 2001-06-27 18:52 ]</font>

 

[nitr8]

is there a VCS v6 roaming around

 

[armer]

I use VCS 6.0.1, I have not fill it is faster than VCS 5.1, maybe my design is small.