Electronics in radiation environment

[engr_joni_ee]

I was reading about single-events and found this statement.

"Single-Event Upsets (SEU): A single-event upset (SEU), also known as a single-event error (SEE), is a change of state caused by one single ionizing particle (ions, electrons, photons...) striking a sensitive node in a live micro-electronic device, such as in a microprocessor, semiconductor memory, or power transistors. The SEU itself is not considered permanently damaging to the transistor's or circuits' functionality unlike the case of single-event latch-up (SEL), single-event gate rupture (SEGR), or single-event burnout (SEB)."

Does this means that SEU is not a permanent damage to the component but SEL, SEGR and SEB can cause permanent damage to the component ?

 

[barry]

You specifically quote “The SEU itself is not considered permanently damaging…” and then ask “Does this mean that SEU is not a permanent damage”

Did you not even read what you quoted?

 

[D.A.(Tony)Stewart]

I was reading about single-events and found this statement.

"Single-Event Upsets (SEU): A single-event upset (SEU), also known as a single-event error (SEE), is a change of state caused by one single ionizing particle (ions, electrons, photons...) striking a sensitive node in a live micro-electronic device, such as in a microprocessor, semiconductor memory, or power transistors. The SEU itself is not considered permanently damaging to the transistor's or circuits' functionality unlike the case of single-event latch-up (SEL), single-event gate rupture (SEGR), or single-event burnout (SEB)."

Does this means that SEU is not a permanent damage to the component but SEL, SEGR and SEB can cause permanent damage to the component ?

Rupture and burnout sounds permanent. These could be from gamma rays or similar energy particles in space outside the magnetosphere or a Carrington effect or massive solar flare.

SEL raised jcn. temp rapidly, and depends on number and Rdson of devices may be reset by a power cycling just like DC on SCR's and detected with current sensing on Vdd.

 

[engr_joni_ee]

Sorry, the question is about SEL, SEGR and SEB. Do they cause permanent damage ?

 

[D.A.(Tony)Stewart]

agreed

single-event latch-up (SEL), single-event gate rupture (SEGR), or single-event burnout (SEB)."
{maybe, usually, usually}
damaged beyond functional use with unknown failure modes.

I haven't seen a SEL event on ESD protected devices but I imagine with the lower RdsOn of modern CMOS, they get a lot hotter than the old C4xxx series since RdsOn is now 20 to 65 ohms depending on Vol/Io=Rdson or rather substrate ESR.

 

[dick_freebird]

SEL may or may not cause permanent damage. It depends on the
heat in (the latched micro-SCR) and heat out (the thermal path, and
if attempting mitigation then also the thermal time constant close-in
to the site).

You can have "micro-latch" events which result only in an elevated
and localized Idd, or you can have a "staircase" of same if the
"victim" features are numerous and discrete, so a continuous
"lighting up" as particles hit their marks.

SEB, "burnout", that's an "end game" observation. Similarly SEGR.
By the time you hear the siren, it's already too late. SEL is a precursor
to burnout, if large and left long enough. But latching itself, is not
-necessarily- fatal. Of course you don't get to know until the bullets
all fail to kill you.

There are other forms of radiation which act similarly but globally,
of which we will not speak in an open international forum.

 

[engr_joni_ee]

What is Rdson ?

 

[betwixt]

Oh dear... I think this is the start of another round of debate over terminology.

Reminds me of a time about 25 years ago when I was asked to design a remote control steering system for a video camera. The spec said temperature range -200C to +200C with rise/fall at 30C per second and very high alpha/beta/gamma radiation levels and in a vacuum. It was to mount on the ISS but the project never went ahead. I wrote to many component manufacturers about extreme environmental conditions and those that replied simply said "you are on your own"! I could insulate, heat and cool devices reasonably easily but those pesky atomic particles are tricky to keep in their places.

Brian.

 

[barry]

agreed

single-event latch-up (SEL), single-event gate rupture (SEGR), or single-event burnout (SEB)."
{maybe, usually, usually}
damaged beyond functional use with unknown failure modes.

I haven't seen a SEL event on ESD protected devices but I imagine with the lower RdsOn of modern CMOS, they get a lot hotter than the old C4xxx series since RdsOn is now 20 to 65 ohms depending on Vol/Io=Rdson or rather substrate ESR.

ESD protection does nothing to mitigate the effects of radiation. ESD protection protects only the inputs of devices; high-energy particles can just crash right through the package.

 

[D.A.(Tony)Stewart]

ESD protection does nothing to mitigate the effects of radiation. ESD protection protects only the inputs of devices; high-energy particles can just crash right through the package.

Perhaps you misunderstood.

I said "I haven't seen a SEL event on ESD protected devices"
I didn't assume ESD protect against SEGR.
SEL events may conducted, radiated or bombarded, if powered on.

 

[dick_freebird]

ESD protection does nothing to mitigate the effects of radiation. ESD protection protects only the inputs of devices; high-energy particles can just crash right through the package.

Not entirely true. I have been called upon to build SGEMP protection
into ASIC designs, and for a low number of harness-exposed pins the
basic HBM ESD protection would have sufficed (per the provided
threat model, which is always a system- and mission-specific one-off).
But I had 300 or so pins that would see about an amp apiece of EMP
current and that required a whole 'nother approach.

It's tricks and trades (and elbow grease) all the way down. With the
occasional freebie (very occasional).

 

[D.A.(Tony)Stewart]

Shielding attenuation is a tradeoff between weight and effectiveness.
The materials vary from gold over copper to lead foil.
How many satellites will be affected by the next Carrington Event?
I wonder how tolerance or susceptibility levels are defined and verified in non-destructive ways. Since Starlink now dominates the active satellites up there, I wonder what design limits they used.

I recall in my 1st job out of Uni. hearing of a colleague whose GOES-1 transmitter under test in a Tenney A/C chamber stuck to the door from duct tape and fell 6" to the tabletop from the oven. NASA engineers calculated the stress levels to crystals and the like and demanded a full rebuild. What if ESD testing causes a gate rupture event but still operates? How would you know how much safety margin was lost?

From this job, I learned how to test my designs for both fragility and EMC. Even TTL back then was ESD sensitive but at a higher level. Most interesting was how I discover how to estimate g shock levels from the ratio of gravity fall height to compliance stop height, verified with accelerometers. We were somewhat naive to EOS practice in the 70's yet observed it between engineers.