sampham04
Junior Member level 2
Hi,
I have a design in Verilog and I used Tetramax to generate test patterns for it, but the version of Tetramax that I have can only write the testbench in VHDL and not Verilog. Does anyone know how I can run a simulation for my Verilog file using a VHDL testbench in VCS or some other Synopsys tool? If you could provide me with a script of how to do this that would be great.
Thank you!
I have a design in Verilog and I used Tetramax to generate test patterns for it, but the version of Tetramax that I have can only write the testbench in VHDL and not Verilog. Does anyone know how I can run a simulation for my Verilog file using a VHDL testbench in VCS or some other Synopsys tool? If you could provide me with a script of how to do this that would be great.
Thank you!