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Mixed Verilog and VHDL Simulation

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sampham04

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Hi,

I have a design in Verilog and I used Tetramax to generate test patterns for it, but the version of Tetramax that I have can only write the testbench in VHDL and not Verilog. Does anyone know how I can run a simulation for my Verilog file using a VHDL testbench in VCS or some other Synopsys tool? If you could provide me with a script of how to do this that would be great.

Thank you!
 

normaly, all the major digital simulator handle properly many language. depending of your license feature, you just need to compile both, and that will work well.
For Mentor, only the compilation is different (vcom / vlog)
 

Are you familiar with VCS? I tried analyzing both the files separately with vlogan and vhdlan and then compiling them with the vcs command, but it compiles the VHDL file like a Verilog file so I get a lot of errors. I also tried compiling them with the scs command instead, but I kept getting an error message about non unification not being supported. I don't have a user manual so I'm not sure what that error means and how I am supposed to go about the compilation.
 

The university that I am at has all the Synopsys tools like Tetramax, Design Compiler, and VCS. We don't have Mentor or ModelSim or anything. If it is not possible to do the mixed simulation with VCS then we may be able to purchase something else, but we would prefer to try to use the tools we already have.
 

first of all, make sure you have VCS-MX rather than VCS. The MX here means mixed simulation support. VCS itself is verilog only.
The compiler for VHDL is indeed vhdlan.
VHDL is similar with Verilog so why are you sure the error messages reported are not real error msgs?
Blame the software after you are certain that the error msgs are non-sense.
Synopsys softwares have good compatibilities between versions. To understand the software, you just need a user manual of any related new version of VCS-MX.
Google it and you can find lots of places where you can get it free.
 

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