DonaldSmith
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mixed signal pld
Several FPGA vendors have mixed-signal FPGAs. I'm interested in learning what applications are best implemented on Actel Fusion FPGA's, and what apps are best suited for Cypress or other vendor's mixed-signal Field Programmable IC's.
In general, the Actel devices are much larger, have more Flash memory, about the same SRAM as Cypress devices. Cypress devices are much less expensive (about $1 (Cypress) compared to approximately $5 (Fusion) in large quantities, 250K), and at first glance, I don't see much Flash memory in the Cypress PSoc. Let me know if I have missed something The large Flash memory allows Actel devices to standby on very low power.
The Actel Fusion has built in scalable inputs. What are the limitations of the scalable inputs, versus discrete pre-scalers? I'm more concerned about the adv's and disadv's spec-wise, rather than the obvious disadvantage of the additional packages and board space.
The Fusion ADC is spec'd at 600 Ksps, so an application that required faster sampling, such as CCD (image) sampling (usually req's about 5 Msps) would not work on a Fusion device. Let me know if you know of exceptions.
The Fusion offers up to 30 scalable input channels. It appears the 600 Ksps have to be shared (allocated) across the inputs. In other words, if all 30 inputs were used, each is allocated 20 Ksps. In a sense, a 1/30th slice of the 600 Ksps. If six were used, each would get 100 Ksps.
Last but not least, "Differential Non-Linearity" sounds a lot like "Differential Linearity Error". The TI ADS804 (a 12-bit, 10 MHz ADC) spec's DLE at 500 KHz at a Max of +/-0.75LSB. The Fusion spec's DNL at < 1 LSB. This seems reasonable, but I'm interested in all opinions.
The ADS804 spec's Integral Non-Linearity Error at 500 KHz at +/-2 LSB, versus the Fusion, which is spec'd at [+/-]0.4 LSB in 10-bit mode. This bothers me a bit that Actel does not provide a 12-bit spec. Does it bother anyone else?
In summary, I'm interested in successful design stories, as well as failures. It would be great to hear what app's worked and with which FPGA. Also, I believe everyone will benefit from hearing about cases where you or your team tried to use a Mixed-signal FPGA and it didn't work out. Sometimes the "tragedies" are more interesting than the "happy endings"!
All the best,
Donald
Several FPGA vendors have mixed-signal FPGAs. I'm interested in learning what applications are best implemented on Actel Fusion FPGA's, and what apps are best suited for Cypress or other vendor's mixed-signal Field Programmable IC's.
In general, the Actel devices are much larger, have more Flash memory, about the same SRAM as Cypress devices. Cypress devices are much less expensive (about $1 (Cypress) compared to approximately $5 (Fusion) in large quantities, 250K), and at first glance, I don't see much Flash memory in the Cypress PSoc. Let me know if I have missed something The large Flash memory allows Actel devices to standby on very low power.
The Actel Fusion has built in scalable inputs. What are the limitations of the scalable inputs, versus discrete pre-scalers? I'm more concerned about the adv's and disadv's spec-wise, rather than the obvious disadvantage of the additional packages and board space.
The Fusion ADC is spec'd at 600 Ksps, so an application that required faster sampling, such as CCD (image) sampling (usually req's about 5 Msps) would not work on a Fusion device. Let me know if you know of exceptions.
The Fusion offers up to 30 scalable input channels. It appears the 600 Ksps have to be shared (allocated) across the inputs. In other words, if all 30 inputs were used, each is allocated 20 Ksps. In a sense, a 1/30th slice of the 600 Ksps. If six were used, each would get 100 Ksps.
Last but not least, "Differential Non-Linearity" sounds a lot like "Differential Linearity Error". The TI ADS804 (a 12-bit, 10 MHz ADC) spec's DLE at 500 KHz at a Max of +/-0.75LSB. The Fusion spec's DNL at < 1 LSB. This seems reasonable, but I'm interested in all opinions.
The ADS804 spec's Integral Non-Linearity Error at 500 KHz at +/-2 LSB, versus the Fusion, which is spec'd at [+/-]0.4 LSB in 10-bit mode. This bothers me a bit that Actel does not provide a 12-bit spec. Does it bother anyone else?
In summary, I'm interested in successful design stories, as well as failures. It would be great to hear what app's worked and with which FPGA. Also, I believe everyone will benefit from hearing about cases where you or your team tried to use a Mixed-signal FPGA and it didn't work out. Sometimes the "tragedies" are more interesting than the "happy endings"!
All the best,
Donald