Mixed-signal FPGAs: What Device Works for Which App?

[DonaldSmith]

mixed signal pld

Several FPGA vendors have mixed-signal FPGAs. I'm interested in learning what applications are best implemented on Actel Fusion FPGA's, and what apps are best suited for Cypress or other vendor's mixed-signal Field Programmable IC's.

In general, the Actel devices are much larger, have more Flash memory, about the same SRAM as Cypress devices. Cypress devices are much less expensive (about $1 (Cypress) compared to approximately $5 (Fusion) in large quantities, 250K), and at first glance, I don't see much Flash memory in the Cypress PSoc. Let me know if I have missed something The large Flash memory allows Actel devices to standby on very low power.

The Actel Fusion has built in scalable inputs. What are the limitations of the scalable inputs, versus discrete pre-scalers? I'm more concerned about the adv's and disadv's spec-wise, rather than the obvious disadvantage of the additional packages and board space.

The Fusion ADC is spec'd at 600 Ksps, so an application that required faster sampling, such as CCD (image) sampling (usually req's about 5 Msps) would not work on a Fusion device. Let me know if you know of exceptions.

The Fusion offers up to 30 scalable input channels. It appears the 600 Ksps have to be shared (allocated) across the inputs. In other words, if all 30 inputs were used, each is allocated 20 Ksps. In a sense, a 1/30th slice of the 600 Ksps. If six were used, each would get 100 Ksps.

Last but not least, "Differential Non-Linearity" sounds a lot like "Differential Linearity Error". The TI ADS804 (a 12-bit, 10 MHz ADC) spec's DLE at 500 KHz at a Max of +/-0.75LSB. The Fusion spec's DNL at < 1 LSB. This seems reasonable, but I'm interested in all opinions.

The ADS804 spec's Integral Non-Linearity Error at 500 KHz at +/-2 LSB, versus the Fusion, which is spec'd at [+/-]0.4 LSB in 10-bit mode. This bothers me a bit that Actel does not provide a 12-bit spec. Does it bother anyone else?

In summary, I'm interested in successful design stories, as well as failures. It would be great to hear what app's worked and with which FPGA. Also, I believe everyone will benefit from hearing about cases where you or your team tried to use a Mixed-signal FPGA and it didn't work out. Sometimes the "tragedies" are more interesting than the "happy endings"!

All the best,

Donald

 

[FvM]

actel versus cypress fpga

If you are referring to Cypress PSoC devices, I didn't think of them yet as Mixed-signal FPGA. They are rather application specific µP with some configurable dedicated hardware. Are there other parts around?

Regarding Actel Fusion, you already mentioned the 600 kS/s total analog throughput. I can't remember of a FPGA project in this slow speed range, it seems to be rather a natural DSP domain. With sufficient fast ADC, it could look promising.

I've been almost convinced by the vendors argument, that it's really difficult to integrate high performance analog on a chip with digital devices. This has been said e.g. about Analog ADuC devices, which are a milestone in slow and medium speed mixed-signal IC design. Thus I think, it can be more interesting to have separate AD/DA parts with smart digital interfaces, e.g. serial LVDS, perfectly matching today's FPGA.

I'm also observing the topic of configurable analog blocks since about 15 years, but I didn't find an application yet, mainly because of their rather poor analog performance.

 

[DonaldSmith]

analog signal fpga

Many thanks for your thoughts. While I believe you are basically correct, I'm hoping someone will tell us about success with mixed-signal FPGA's. Cypress claims to have shipped billions of the PSoC mixed-signal FPGA's.

Actel claims success with Fusion to speed the design of advanced Telecommunications Computer Architecture (TCA) blade and carrier blade management controllers and systems.

Another success with Fusion is in a position detection encoder for servo motors for industrial applications, and it was selected for its low power and high accuracy. The Fusion device was used in the main process circuit, converting signals from the resolver into position data.

These applications do seem to fit the mold of low-speed ADC, correct?

All the best,

Donald

 

[oursriharsha]

mixed signal fpga

As i have started recently working with the ACTEL Fusion (AFS600),
i found the ADC performance is not to the mark .

 

[DonaldSmith]

low power mixed signals fpgas

By "performance is not to the mark", do you mean the chips do not meet the specifications? What spec's do they not meet? Do the chips meet any of their spec's?

Donald

 

[anithatg]

what is mixed signal device main specification

Regarding PSoCs, they are not mixed signal FPGAs. They have configurable digital and analog blocks which you can configure for your applications. Due to this integrity, they can increase the functionality, thus reducing the board space and the chip count for your application.