mixed design in Lattice ispLever

[davorin]

Since ispLever Base 4.1 doesn't support mixed language designs..

How can I incorporate a VHDL CPU core for example into a Verilog design?

 

[lucbra]

I haven't tried it yet, but they told me to compile VHDL and Verilog files separate, build the edif netlist, and afterwards build together.

 

[davorin]

Well..only way seems to be via synplify pro....but who can afford it anyway? (o;


Or can I import several EDIF subdesigns into ispLever?

 

[eBond]

Yes it doesnt support mixed mode but you can use anyother tool for initial steps like Aldec or rivera .. if you need teh software lemm know and and once the EDIF is done then you can start using Lattice ispLEVER 4.2 or preffered 5 .. thatsis good easy tool ...
performanceis awesome
Bond

 

[davorin]

Yes it doesnt support mixed mode but you can use anyother tool for initial steps like Aldec or rivera .. if you need teh software lemm know and and once the EDIF is done then you can start using Lattice ispLEVER 4.2 or preffered 5 .. thatsis good easy tool ...
performanceis awesome
Bond

Stop flooding here with Lattice advertisment and software offering!!