Minimun depth of an asynchronous FIFO

[fragnen]

What is the minimum depth of an asynchronous FIFO and why that should be the minimum depth? I mean if there is any depth below which we cannot get an asynchronous FIFO.

 

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2
That will only work if the clocks are asynchronous but the same frequency (and there is enough dead time to account for frequency drift between the clocks, unless they are locked), otherwise it needs to be 4 or greater depending on the fill/drain rate difference.

You need to study the fill/drain rate problem. That is the basis of any FIFO design depth calculation.

 

[fragnen]

So let me frame the question again.

What is the minimum depth of an asynchronous FIFO when write and read clock frequencies are same and why that should be the minimum depth?

 

[ads-ee]

Draw a timing diagram and analyze it.

It appears to me you aren't very motivated to do your own research and analysis and want others to do it for you.

 

[fragnen]

Draw a timing diagram and analyze it.

It appears to me you aren't very motivated to do your own research and analysis and want others to do it for you.

Can you please provide some more hints?

 

[ads-ee]

Draw the timing diagram and analyze it. You don't need more hints, we've already told you what you need to do.

Do you know how to draw a timing diagram or analyze a digital circuit?