On 2002-02-04 14:41, hwswboy wrote:
Well..., the background fact is that i want to do place-and-route and floorplaning because i have more ASIC designs in the near future, and outsourcing part of the designs is not the way.
.... i'm not in the beginner stage, as you can think floorplanign in a virtex II (near 1 million gates) is not like a CPLD :wink:
The situation is i want to share information and experience with people doing ASIC designs.
On 2002-02-05 10:49, hwswboy wrote:
cdic: Thank yo for your oppinion.
Yes, I know I have a HARD MISSION, but is part of my everyday work in a R&D lab :wink:.
I have the teorical knowelge (some and some VLSI, ASIC,.. books readed), but for me is the time to change. I know all the problems involved in ASIC design, and i know the differences with FPGA, but is the time.
..... I hope 17+ years in electronics industry and 8+ years of experience in VHDL&FPGA with several real designs from 50K to 1M gates in complex apps will be enought start point :wink:
All oppinions are wellcome :smile:
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