migrating FPGA to ASIC - some questions

[hwswboy]

In the next months i have to migrate a FPGA VirtexII VHDL design (near to million gates) to ASIC.

In the original design i use a classic FPGA flow using as main tools Synplify+Amplfy+Modelsim, but i think boundary conditions,timing constraints and layout (even synthesis) in ASIC will be very different and other flow and considerations will be used.

I want to open some questions:


1.- Synthesis whit ASIC vendor libraries will become more different than FGA ones? switching from Synplify (or Leonardo) to DC are the best option?

2.- What are the best tools for P&R, Floor Planning, Layout?

3.- Modelsim will be enought for Post-layout Simulation?

4.- What flows do you use in real million gate designs?

5.- Anyone with experience in real world migration from FPGA to ASIC in million gate designs?

6.- NRE Costs?

7.- Any fundamental questions :wink: ?


Any comments will wellcome, thank you in advance.

*****************************************
Please don't reply unless you have useful information to add on this post.Thanks

 

[litv]

For example **broken link removed**.
DLL and memory supported.
But they want ~300000$. Stupid company.

Easy from VHDL by Cadence(all tools) to ASIC
independently.
Any ASIC company can help you.
If your project with big volume - without money for conversion.

 

[buzkiller]

Hi hwswboy,

1) If you used Synplify for FPGA synthesis, you better use it for ASIC too.
Stay with the tool that you know.

2)Leave place-and-route and floorplaning to your ASIC vendor. It's not a task
for beginners.

3)Modelsim SE should be enough, also try Riviera from Aldec. On Linux, of course.

6)The safest solution is to give your design to companies that specialize in
FPGA to ASIC migration. You'll find plenty of such companies here :
https://www.google.com/search?hl=en&q=FPGA+to+ASIC+conversion

It might cost you same or even more than to buy the tools and do it yourself, but at
least you know it will work.

regards,
Buzkiller.

 

[hwswboy]

Well..., the background fact is that i want to do place-and-route and floorplaning because i have more ASIC designs in the near future, and outsourcing part of the designs is not the way.

.... i'm not in the beginner stage, as you can think floorplanign in a virtex II (near 1 million gates) is not like a CPLD :wink:

The situation is i want to share information and experience with people doing ASIC designs.

 

[hwswboy]

Hi aladdin, if you don't have inconvenience i think this is the PLACE to speak, perhaps more people have the same problem, or the questions are interesting itself for other members.

I think this kind of post are value added for elektroda.... i'm tired of "software collector" posts. I recognize that "tools" are behind this kind of questions, but what are tools without the addecuate background knowelge ......

Other 2 cent. thinking .... only "top" post are readed? .... :wink:

<font size=-1>[ This Message was edited by: hwswboy on 2002-02-04 15:53 ]</font>

 

[cdic]

hwswboy:
doing the floor-plan and placement for IC design is really not a easy work to do. It's not similar as the FPGA design, You have to handle tons of things, for example: vendor library setup, design-rule setup, design environment setup, and as to your design ~1M, it's not a small design, you must also take the die size,timing,power,SI in consider, you also need to choose your power distribution strategy, PAD cell...... many many thing need to be considered. All I list above is just only part of the job. The floor-plan and Placement is the most important stage in the whole back-end flow, if you make any wrong decision/fault, you need to pay much more time/cost to correct it than in the following stage. You REALLY need time to study if you want to do it by yourself. HARD MISSION if you have no experience in IC Design.

Good Luck
cdic

On 2002-02-04 14:41, hwswboy wrote:
Well..., the background fact is that i want to do place-and-route and floorplaning because i have more ASIC designs in the near future, and outsourcing part of the designs is not the way.

.... i'm not in the beginner stage, as you can think floorplanign in a virtex II (near 1 million gates) is not like a CPLD :wink:

The situation is i want to share information and experience with people doing ASIC designs.

 

[hwswboy]

cdic: Thank yo for your oppinion.

Yes, I know I have a HARD MISSION, but is part of my everyday work in a R&D lab :wink:.

I have the teorical knowelge (some and some VLSI, ASIC,.. books readed), but for me is the time to change. I know all the problems involved in ASIC design, and i know the differences with FPGA, but is the time.

..... I hope 17+ years in electronics industry and 8+ years of experience in VHDL&FPGA with several real designs from 50K to 1M gates in complex apps will be enought start point :wink:

All oppinions are wellcome :smile:

 

[xirix]

I think the best solution is Cadence: tools for floorplan and Silicon Ensemble for standard P&R. You need tech/timing libraries...
It is best, but ...money.
A cheaper solution is Monterey Design:
ICWizard - floorplanner
Dolphin - P&R
The last is a very nice tool, not like SE, but you'll have all job in "a push button" idea. And the timing, constraints are in synopsys format.

If you didn't do such a job until now, you must have or see a good example maided by another one.

 

[heat]

hi,

hope my questions to that theme do not sound to stupid.

Is is right if i use VHDL-code to discribe my circuit, i have two options:
1) to implement it on an FPGA
using for example Xilinx with FPGAExpress
or Synplicity or Exemplar or XST ... and
the internal P&R-Tool

2) to implement in on an ASIC
(never done that before ...)
using for example Syplicity ASIC
and a tool for P&R (maybe someone can
tell me witch ones are fine?)

Am i right with these two ways to deal
with VDHL-Code? My designs at this point
are about 10K to 100K so definetly "very"
small. And i implement them on FPGAs. But
i am interested in how to implement them
on an ASIC to get them faster. Maybe someone
can give me a good link or tips about that.

Thankx Heat :smile:

 

[cdic]

hwswboy:
I know your situation now, seems that you have a real good start-point. :smile:
My Advice:
1. Pay more attention to the synthesis, try to get a golden gate-level netlist. and then do the dft, test insertion and test vector generation. (For FPGA , you don't need to do that). and don't forget the pad module also should be in your gate-level netlist, cause pad cell also consume the timing, you should use it for the STA or Gate-level simulation.
2. Choose your back-end flow, choose your P&R tool. I recomment Monterey tool also, it's easy to converge to the timing closure, don't need to swith to other tools often to get the result, less iteration. but now the Silicon-Ensemble and Apollo are still the industry standard flow. If you have enough money/time/resource/support, you should choose one of them.
3. try to find a teacher, books couldn't help you to fix the real problem, it can only tell you the direction. you need help to fix these problems, I don't mean that you are not smart, but in sometimes you really don't know how to do until you did it once.

Good Luck
cdic

On 2002-02-05 10:49, hwswboy wrote:
cdic: Thank yo for your oppinion.

Yes, I know I have a HARD MISSION, but is part of my everyday work in a R&D lab :wink:.

I have the teorical knowelge (some and some VLSI, ASIC,.. books readed), but for me is the time to change. I know all the problems involved in ASIC design, and i know the differences with FPGA, but is the time.

..... I hope 17+ years in electronics industry and 8+ years of experience in VHDL&FPGA with several real designs from 50K to 1M gates in complex apps will be enought start point :wink:

All oppinions are wellcome :smile:

 

[buzkiller]

Hi hwswboy,

When I said that ASIC P&R and floorplanning is not a task for beginners , I meant
beginners in ASIC field. And you are definitely a beginner.
While FPGA and ASIC synthsis has a lot in common, and can be performed in similar tools
(FPGA Express - DC Compiler, Synplify PRO - Synplify ASIC), P&R and floorplaning tools
and technics are very different.
You shouldn't start by making a million gate ASIC.
Here is what i offer you:
1) Make the synthesis yourself.
2) Outsourse P&R and Floorplanning. Ask what tools they use, and ask the tool vendors
for a course and evaluation copy of the tools.
3)You'll probably have to spend some time at your P&R vendor(outsorser) site, to help them.
So while you are there, you can see how they do it on your design and learn from it.

This way, you'll acquire an experience, that will be helpful for your next design,
at no extra cost (risk).

regards,
Buzkiller.

 

[nmtr]

Hi hwswboy:
why do you want to do all thing by yourself,in my opnion,you have lots of expriences and now you should be a mananger or master in your departmant,the thing you have to do is that asking your fellows to the detail thing like the synthsis or P&R,DFT and so on,not do anything by yourself,just use your experinces to directe your fellows to do detail things,you should only know the design_flow,the theory,the basic function of the tools.NOT WASTE your expensive time to learn a now tools,the expericense is the best thing your have.

Quote:
--------------------------------------------------------------------------------


..... I hope 17+ years in electronics industry and 8+ years of experience in VHDL&FPGA with several real designs from 50K to 1M gates in complex apps will be enought start point.
hope my idea do not sound to stupid 8

 

[ramo]

i'm in the beginner stage and I have a same questions !!!
All the best,
ramo

 

[hwswboy]

nmtr:

YES, you are right, i'm the R&D dpt. leader and 50% of my work is to directe fellows. But in my thinking is the fact that you need to know things before you directe things.

As you can think, i don't do all work, and i have my own opinions in synthesis,P&R,DFT, tools, etc. but i think here a some people involved in ASIC and i want to hear some oppinions and share experience :wink:

 

[bigbrother]

If we had the 'Top Thread of the Week' this is the one that I would chose!!

I can say with certaintly that this is the first thread that I liked so much that I will archive it to my PC.

I am very new in this field of design, but posts like these are very interesting for me, because they are problems that I may encounter with some time.

Unfortunattely I cannot help here, but I will be watching this more than interesting thread!

Keep up the good work!

 

[nmtr]

i think first thing you have to do is choosing a good vendor(fundry)with good services,reliable std_library,proper prices,advanced process.which process suits for your current and future's projects( of course it is not very long).
example:
Choose the 0.25um or 0.18um cmos process with six aul layer or high.not chose 0.3 um four aul layer process which is out of times.and results in big die area,huge power consume,low frequency.
choose a good vendor's with good credit standing,good servicse.they can provide reliable std_library,detailed describes of process,reslove the problem you are meeting.give good advices, even they can point out the mistakes in your layouts.
once you choose a vendor,be familiar with its process and std_library,and acquire the expricenses in synthsis to get a golden netlist.
most of fpga use macro cell,not the simple gate, so the artist of synthsis may be different.and the libraries of vendors are different too.some of them are big contain one or two hudred types of cells,some are small only contain 30-50 types gates.if you think the exprience of synthsis is very important,don't change your vendor and process if not very necessry.
follow the vendor's advice in choosing the design tools is a good idea.some vendor only provide help information for cadence's tools,some may provide more.
of course the prices is important too.
now our university choose the umc 0.25um six aul process.
by the way, some vendor can provide layouts services, you can only focus on the work of synthsis and testing.

 

[heat]

hi

that is too much ... it seems people answering to that post know what there talking about. And my question (above) seems
to be dammed to nowhere land because it is to low ... i don't knwo but i hoped that someone could anwser and help me somehow ...

Thankx

 

[hwswboy]

Please continue in the new ASIC forum.

Thank you in advance.

 

[Robin Hood]

Topic is now in the ASIC forum.

 

[net_light]

surely cadence tool sets will give you great help.
I use SEPKS from rtl to GDSII and Virtuoso+Assura to final tapeout.
in SEPKS, you can do logical and physical synthesis + lowpower and datapath optimization, then easy to getthe golden netlist + same constraints + legal placement
and the global route database to let their final router called wroute finish detail routing. in this flow, you can even fix SI problems as cadmos crosstalk analysis engine also included. do all major things in one box greatly help me get the best performance chip. only one point: the price seems high at the beginning. but actually this is the cheapest one. as you do not need have expensive DC and Appolo now. even the full chip timing engine and the dft is included in this package. and we add Syntest ATPG to
get the test patten.
and the synthesis speed and capacity is about 10X than DC, this saves a lot of time for me, now our R&D is plan to replace all DC
to PKS.
and SEPKS support 64 bits. but only for flatten design. our designs is about 1M to 5M gates. I saw a company tapeout 10M design.
now we focus on hier. design flow. seems SPC
firstEncounter is a good choice.we plan to use it in next 8M gate design.