hastidot
Junior Member level 3
Hi all
I am using MIG as a DDR2 controller for viretx5. I know that the FPGA's RAM's function has some problems in some memory addresss. I'm oing to detect those addresses. I'v generated the design . But after using chipscope, I found the error signal aways being asserted and there are no valid data on the rd_data_fifo_out (rd_data_valid sometimes goes high).
As the UG086 document indicates, after the licked signals activates, my design is in reset mode for 30 clock pulse.
The phy_init_done is always asserted.
I don't know what is the problem with my design that there are no valid output data. :-(
I am using MIG as a DDR2 controller for viretx5. I know that the FPGA's RAM's function has some problems in some memory addresss. I'm oing to detect those addresses. I'v generated the design . But after using chipscope, I found the error signal aways being asserted and there are no valid data on the rd_data_fifo_out (rd_data_valid sometimes goes high).
As the UG086 document indicates, after the licked signals activates, my design is in reset mode for 30 clock pulse.
The phy_init_done is always asserted.
I don't know what is the problem with my design that there are no valid output data. :-(