Memory verification using testbench.

[muthuram1984]

Hi all,

Please explain how we can verify a Memory using testbench?..For example
i am writing data to a location 10 and reading from that location.but it is giving the data from the location 20......
so how can i verify that?

Thanks
ASICan

 

[shaiko]

What HDL are you using?

 

[muthuram1984]

What HDL are you using?

I am using Verilog HDL.But my doubt is how can we bring up this memory read problem using verilog test bench?
We can randomise the Address,payload data by using random constructs aparat from that how can we bring up this issue using our test bench?

Thanks
Muthu

 

[shaiko]

Basically a testbench is a "wraper" of your module.
You drive signals to the input and see the waveform of internal logic and outputs.

I don't speak Verilog very well.
Do you know VHDL ?

 

[jeet_asic]

Can you post your Verilog code? it would b much easier to answer.

Hi all,

Please explain how we can verify a Memory using testbench?..For example
i am writing data to a location 10 and reading from that location.but it is giving the data from the location 20......
so how can i verify that?

Thanks
ASICan

 

[smashash147]

Instead of using HDL for verification go for HVL(hardware verification languages such as specman e/system verilog and specifically for memory verification you need to incorporate a checker in your testbench that will verify automatically wether the sent packet was reaed accurately from that particular memory to identify the correct data you can take addresss a s a reference and also append a CRC bit to make the comparison much better.

 

[logiclife]

try like this

very first in verilog itself write a test bench.

use a concept called driver which it inter relates tb and your dut

in that driver concept you write all the routing connections
if you are good in writing tasks and functions write them in driver.

now write an another module : checker
now compare the the out put of test bench with driven values with respect to address

---------- Post added at 19:29 ---------- Previous post was at 19:25 ----------

instantiate all the modules in test bench this is important thing
instantiate dut,driver,checker
beware of port mapping.

checker:u can write effective way of checker by writing a model and compare the two outputs