affreen
Newbie level 3
Paper is to be coded in digital,so when SRAM is tested using MBIST,SRAM has to be designed in verilog.So if its possible to design SRAM in verilog,then how is it so..
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yea.it is possible to design sram in verilog,
pl look at this : http://www.actel.com/documents/rtl_memory_an.pdf