I want to know what is the maximum input voltage we can give on a MOS device (A CMOS or anything) without damaging it.
Let us consider a simple CMOS invertor, with vdd=1.8 V. I simply need to know does vdd decides the maximum input or which other factor is involved.
Where are you giving this maximum voltage? if it is on gate, gate oxide thickness will decide its value. foundry datasheet should provide these information.
Where are you giving this maximum voltage? if it is on gate, gate oxide thickness will decide its value. foundry datasheet should provide these information.
I am giving this input to gate.....n yes I know foundry datasheet provide this information, but I was interested in knowing the parameters which decides this voltage. Actually I have a theoretical assignment, in which one invertor drives the other.....However, the vdd of second is 1.8V and for first is 3V. So I want to know if gate voltage of second invertor can be more than 1.8V (say 2.8V)..?
I guess the threshold of these inverters are diff.
So one switches one with 1.8 and the other with 3v.
U cant give 2.8 for the inv with max gate voltage of 1.8 as this would break the oxide and damage the cell.
I guess the threshold of these inverters are diff.
So one switches one with 1.8 and the other with 3v.
U cant give 2.8 for the inv with max gate voltage of 1.8 as this would break the oxide and damage the cell.
Thanks for the reply. Exactly this I wanted to hear.
I am working on noise margin and have a circuit like this....My perception was the same as your's and I guess this is the correct and apt answer.
Lets see, I will update once I get results of my assignment.