Master data width is more than slave data width in Altera/Intel Qsys AXI bridge
Hi all!
Currently I am working in Quartus 17. I have created AXI bridge-based system in the Qsys, where data bus for both master and slave sizes is 32-bit. Now I need to increase AXI bridge data width to 128 bit (master side), but some of my slave devices have 32-bit data bus. I have found in "Qsys Interconnect" pdf (chapter 7, pp.61) that this situation (master data width > slave data width in AXI Bridge) is not supported by Qsys (is it right?). So, the question is how to handle this situation?
You probably have to create a custom component that functions as an AXI 128-bit to 32-bit bridge, as I don't use Intel I'm not sure if there is a better way to do this.
Yes, I already tried to implement AXI interconnect with 128bit master<->32bit slave, and it does not work. Then I have searched in the Intel documentation, and found in "Qsys Interconnect" pdf (chapter 7, pp.61) that this situation (master data width > slave data width in AXI Bridge) is not supported by Qsys (as I understand!). Please, correct me if I am mistaken and there is an opportunity to do this using Qsys. That is why I ask here - to be sure.
Yes, I already tried to implement AXI interconnect with 128bit master<->32bit slave, and it does not work. Then I have searched in the Intel documentation, and found in "Qsys Interconnect" pdf (chapter 7, pp.61) that this situation (master data width > slave data width in AXI Bridge) is not supported by Qsys (as I understand!). Please, correct me if I am mistaken and there is an opportunity to do this using Qsys. That is why I ask here - to be sure.
You write your own VHDL/Verilog design that has a 128-bit AXI slave interface which connects to a 32-bit AXI master interface. That custom design does the bus width conversion by spacing out the 128-bit transaction to 4 32-bit transactions.
I did not say to use a Qsys component or anything from Qsys to implement this.
In Xilinx land you would create a custom component and then use their tools to create a library component that ends up in their catalog, which you can then instantiate in a block design schematic. I'm sure Intel has the same type of tools. Start reading the documentation.