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Master data width is more than slave data width in Altera/Intel Qsys AXI bridge
Hi all!
Currently I am working in Quartus 17. I have created AXI bridge-based system in the Qsys, where data bus for both master and slave sizes is 32-bit. Now I need to increase AXI bridge data width to 128 bit (master side), but some of my slave devices have 32-bit data bus. I have found in "Qsys Interconnect" pdf (chapter 7, pp.61) that this situation (master data width > slave data width in AXI Bridge) is not supported by Qsys (is it right?). So, the question is how to handle this situation?
Thank you in advance!
Hi all!
Currently I am working in Quartus 17. I have created AXI bridge-based system in the Qsys, where data bus for both master and slave sizes is 32-bit. Now I need to increase AXI bridge data width to 128 bit (master side), but some of my slave devices have 32-bit data bus. I have found in "Qsys Interconnect" pdf (chapter 7, pp.61) that this situation (master data width > slave data width in AXI Bridge) is not supported by Qsys (is it right?). So, the question is how to handle this situation?
Thank you in advance!