[SOLVED] Xilinx IP Core with native data in and AXI bus data out

[FlyingDutch]

Hello Forum,

I have written a design wich produce periodically some data. Data has parallel form 28-bit of data. There also is "strobe" signal (active High) which means that data should be transferred. I am searching for Xilinx Vivado IP Core which on one side has just "native" parallel data and on the second side has AXI bus. Ultimately I would like to send this parallel data in burst by 8 packages. i mean I have stored 28-bit X 8 array and when strobe goes high then I want to send this array by AXI bus in burst mode of length 8. AXI data will has width of 32-bit. What Xilinx IP Core best fits with described behavior?

Thanks in advance and Regards

 

[TrickyDicky]

Axi streaming or axi4 full or lite?

 

[ads-ee]

Axi streaming or axi4 full or lite?

Given the requirements it is an AXI4 full, since the requirement is a burst transfer of 8.
Streaming isn't a burst interface and Lite doesn't support burst.

There won't be a AXI4 bridge interface as you described in Xilinx's core library, you will have to write one.
On your user interface side write the 8 data words to a FIFO, when you have 8 words start an AXI4 burst transaction.

You should download the AMBA AXI4 spec if you haven't already.

 

[TrickyDicky]

@ads-ee AXI4 FUll also requires the use of Address and data buses. The OP specified no information about how or where the data is transfered. AXIS has byte enable signalling as well as packet transfers (or bursts). So my question is still valid - do you want to use AXIS or a memory type transfer via AXI4 ?

 

[FlyingDutch]

@ads-ee AXI4 FUll also requires the use of Address and data buses. The OP specified no information about how or where the data is transfered. AXIS has byte enable signalling as well as packet transfers (or bursts). So my question is still valid - do you want to use AXIS or a memory type transfer via AXI4 ?

Hello,

first sorry for delay in response. Yes my post hadn't been precise. First I thought about transfer data in burst (DMA) mode by AXI 4. But I made trial wit AXI Lite (single) transmissions, and it is fast enough, so I give up with DMA mode. I just wrote code for handling signals for AXI Lite bus, and it is working OK. I transfer data from PL to PS in Zynq-7000 SoC.

Thanks for answer and regards