LVS problem in nfets in ibm process

[tromeros]

Hello,

I am designing a LNA circuit using IBM 0.5um sige5am process. I am in the LVS process. I face the following problem.

In my design I use both nmos kai pmos transistors.
The pmos (pfetx in the process) has four terminals both in design and the layout and passes the LVS check without problem. The fourth terminal is the nwell contact which is connected to the vdd.

The nmos (nfetx in the process) has four terminals in the schematic but 3 in the layout so it gives LVS problem. The 4th contact which should connect to the substrate doesn't exist in the layout view of the nfet.

If anyone has used this process please help!
Thank you very much guys, i appreciate your hepl.

 

[Troy]

In the cmos process I'm currently using the bulk conection for the nmos also isn't included in the pcell. This is because the nmos bulk connection is also substrate connections. You need to add substrate connections near the nmos for LVS.

 

[sriganapati]

Yes,you need to draw p-tap near to nmos and connect that to vss.

 

[tromeros]

Troy,
if i use a substrate contact (subc component) I get the LVS error that in layout there is an additional component (subc) that does not exist in the schematic. So if you can give me more details that would be nice.

Thanks a lot.

 

[Troy]

I'm not sure why it is giving you that error, I am not using that process/PDK. Adding the substrate contacts is how it is corrected in the process I am using.

 

[doho]

Troy,
if i use a substrate contact (subc component) I get the LVS error that in layout there is an additional component (subc) that does not exist in the schematic. So if you can give me more details that would be nice.

Thanks a lot.

Seems like you have forgotten to add the subc component in your schematic.

 

[tromeros]

Hello friends
I continue this post since I haven’t yet managed to carry out a successful lvs using a single nfet (nfetx) in the ibm sige5am process. When I use pfetx I get a successful lvs check.
I use a subc in the schematic and the layout. The difference in the netlist is that the nfet in the schematic has 4 connections while that in the layout has 3 connections.

I know that the body of the nfet is the same as subc but I get the above error.

If someone has used this process please inform me how to resolve this problem.

Thanks again!