tromeros
Member level 1
Hello,
I am designing a LNA circuit using IBM 0.5um sige5am process. I am in the LVS process. I face the following problem.
In my design I use both nmos kai pmos transistors.
The pmos (pfetx in the process) has four terminals both in design and the layout and passes the LVS check without problem. The fourth terminal is the nwell contact which is connected to the vdd.
The nmos (nfetx in the process) has four terminals in the schematic but 3 in the layout so it gives LVS problem. The 4th contact which should connect to the substrate doesn't exist in the layout view of the nfet.
If anyone has used this process please help!
Thank you very much guys, i appreciate your hepl.
I am designing a LNA circuit using IBM 0.5um sige5am process. I am in the LVS process. I face the following problem.
In my design I use both nmos kai pmos transistors.
The pmos (pfetx in the process) has four terminals both in design and the layout and passes the LVS check without problem. The fourth terminal is the nwell contact which is connected to the vdd.
The nmos (nfetx in the process) has four terminals in the schematic but 3 in the layout so it gives LVS problem. The 4th contact which should connect to the substrate doesn't exist in the layout view of the nfet.
If anyone has used this process please help!
Thank you very much guys, i appreciate your hepl.