This or similar sentence we often see here. But if demo board works, and your board not, so most likely there is a difference.My schematic is essentially the same as the demo board.
Does this mean, the demo board uses a two-layer PCB without thermal vias for the MOSFETs?I tried to make my PCB layout similar to the demo board
Hi,
Why did you connect a capacitor to the I_Lim pin?
It's meant to use a resistor...
Klaus
Does this mean, the demo board uses a two-layer PCB without thermal vias for the MOSFETs?
I also think that using 100V, 40 mohm@4.5V MOSFETs isn't the best option for 28 V input. But the converter should at least work with 2.5A output with acceptable heating, so there's probably a different problem.
In a first step I would thorougly look at switching waveforms while the load increases.
Is it just me or is there a stupidly massive split in the ground plane between the chip and the power side particularly near the input side of the thing?
You should never route a high speed, heavy current signal over a split in its reference plane, and some of the stuff you have going on here falls into that category.
The split was my attempt to separate analog and power ground planes, as suggested in app notes, to prevent switching currents within analog ground plane. I sunk all analog ground points at the ground plane which is split from the one where high currents flow. I never done 4 layer boards, so this was my attempt to stay with 2 layers and separate analog and power paths. Maybe I did not do it correctly, but could it explain massive overheating of FETs I am seeing? Would it be better to remove the split and merge all grounds together?
Ref TI datasheet.High currents and excessive parasitic inductance can generate extremely fast δV/δt times during this transition. These fast δV/δt transitions can sometimes cause avalanche breakdown in the synchronous FET body diode, generating shoot-through currents via parasitic turn-on of the synchronous FET.
Layout practices and component orientations that minimize parasitic inductance on the switched nodes is critical for reducing these effects.
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