Continue to Site

# Switching loss for Synch Buck?

#### cupoftea

Hi,
Just downloaded the Synch Buck calculator from ti.com, and for one of their synch buck chips,
i got it to calculate the switching loss. It said top FET switching loss was 2.7W....

NFET CSD18533Q5A was bottom FET
NFET CSD18563Q5A was top FET

Buck was 12.5A out, 13v5 out, 27V5 Vin , 450kHz.

ti.com Synch Buck Switching Loss calculator....

They give the equation for the switching loss, which indeed is the correct one, but that equation does not give 2.7W for switching loss.
It gives less than 0.5 Watt.

I also calculated the switching loss in the manner described in the document by Laszlo Balogh...

..and again, the figure comes out nowhere near 2.7W.

As you know the principle for finding FET_ON switching loss is simple...
..You find the power for two time periods..
1...Time to charge Ciss from Vgs(th) to Vgs(i_pedestal) [i(pedestal) is the "valley" of the inductor current]
2...Time to discharge Cds from Vin to Zero. (Qgd ends up getting used here)

...Both calculations are ultimately from dt = C.dv/i(drive)

where...
i(drive) is the current sourced by the driver, to find which, you need to know the drive output voltage
and the drive series resistance. (And also the "average" gate voltage over the time interval concerned).
-And then its Ohms Law.

Anyway, with the FET_OFF switching loss calculated in the same vain, it comes out as less than 0.5W..

So how did ti.com come up with 2.7W?

Must admit the driver source and sink resistances are low, and i believe on the real product we will have to add series
gate resistance, otherwise the FET will hard-switch too fast, and resulting noise could ruin the operation.

#### Attachments

• Synch Buck switching loss.png
65.7 KB · Views: 32
• Synch Buck switching loss.zip
2.6 KB · Views: 25

Hi, Sorry my switching loss was out by a bit as i typo'd the gate series resistance
in too low...but with this corrected, its still
nowhere near 2.7W, so i wonder how they came up with this figure?

The interesting thing is the Qgd of the CSD18563Q5A. This is just 2.9nC (as at datasheet condition of VDS=30V).
With the LTC3890, the upper gate drive source resistance is 2.5 Ohms.
At 10A (inductor current at Turn on time), the VGS of the upper FET will be 3.1V.
So 3.1V is the miller plateau level.
And it follows that the gate drivers sourced current is (5V-3.1V)/2.5R = 0.76A
So the "Miller plateau time" = t = Qgd/0.76 = 2.9nC/0.76 = 3.8ns. [Result].

..As you can see, 3.8ns is a very short time for the Vds to smash from Vin to 0V.
That would cause noise issues, and so we will need an extra ghate series resistance.

Anyway, the "current rise interval" is simply given by dt = C.dv/i
where
C = Ciss
i = gate drive for this interval (= 5V-2V)/2.5 = 1.2A.
dv = 3.2V - 2V (ie the difference between VGS(TH) and VGS(miller).

So this 1.2A will charge the 1.15n (Ciss) over 1.2V in dt = C.dv/i = (1.15n x 1.2) / 1.2 = 1.15ns [result]

The VI/2 product in both intervals is 27*10/2 = 135W

Multiply this by (3.8ns + 1.15ns) = 4.95ns, to get the energy per switching period = 135 * 4.95n = 668nJ
..Multiply this by f(sw) [450khz) to get turn on switching loss = 0.301W

It works out as 0.157W for the Turn off, so total switching loss = 0.458W.
But the ti.com calculator gives it 2.7W. Do you know what they did?

I would admit that 2.7W sounds a more reasonable number, but it cant be that high without increasing the
gate series resistance.

Its suspected that ti.com have put in a correction factor for the stray inductances, but do you know what they might have done for this?

Last edited:

Source resistance does not tell the whole story, when
Vds > Vgs you see higher Zdrain (quasi-constant-current).
Not VIN/Ron, until VSW < Vgs (or thereabouts).

And parasitics....

Thanks, and as you now, this is a buck, so at switch_ON, the current being switched is i(valley) and at Switch_OFF, the current being switched is i(peak)

where:
i(peak) = peak inductor current
i(valley) = valley of the inductor current

I actually think the reason that the entire switching loss overlap calculation method as detailed by Laszlo Balogh is way off, is, as Balogh himself alludes, due to the stray inductances in the layout of the circuit.

In truth i dont really believe that an accurate model for switching losses in a synch buck can be derived within the normal time-frame and cost-frame of a typical power supply project for synch Buck.

When I was doing the POL DC-DC chips we had a smart kid on the team who made an Excel 'sheet with every damn thing figured. He worked by calculating individual loss mechanisms to get each one's "contributed inefficiency" which all rolled up and flipped, gives you efficiency - but having each aspect plain, let us focus on the loss elements that mattered most.