Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

LTC4020 buck/boost battery charger - troubleshooting

Status
Not open for further replies.

electric1

Junior Member level 2
Joined
Apr 23, 2011
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,507
Hi,

I built a prototype of battery charger, using LTC4020 which fits many of my requirements. I also have their demo board which proves that it can work in my application, 4S LiFePO4 battery, 14.4V CC/CV charging profile, 8A current limit.

My experience is with low power digital circuits and MCU programming, I don't have much experience with PWM power circuits, although I built a few simple buck converters before, with various success. This is my first project at ~100W power level and I need high efficiency due to small project footprint and limited airflow for cooling.

I tried to make my PCB layout similar to the demo board, followed application notes as much as I could, etc.

In the end my prototype seems to be functional without a load, i.e. it holds correct output voltage, I can see PWM forms on my scope, they seem to be similar to signals observed on the demo board, but as soon as I apply the load, even 2-3 Amps, my FETs heat up within few seconds forcing me to cut the load to prevent burning up FETs.

I tried few different FETs, same and similar to what demo board has and what is recommended in app notes. Selected FETs for low Qg and low RDSon balance, which I believe is important to minimize both switching and conduction losses. Same results every time, immediate heating up of FETs, bottom ones heat up noticeably faster than top ones.

I use the circuit as buck in my testing, input voltage is 28V, output is 14.4V

Any advise how to troubleshoot this problem? My schematic is essentially the same as the demo board.

I'm even willing to pay someone with experience to help me, but I don't know if its against the rules here or how to even approach such engagement.
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
19,772
Helped
4,350
Reputation
8,709
Reaction score
4,314
Trophy points
1,393
Activity points
130,852
Hi,

My schematic is essentially the same as the demo board.
This or similar sentence we often see here. But if demo board works, and your board not, so most likely there is a difference.
A review by a second person is always a good idea.
Not only schematic, but also pcb layout and parts selection may cause problems
( especially inductor saturation, electrolytic capacitors and wirewound resistors).

Therefore I recommend to post the schematic, pcb layout and additional informations on parts.

Klaus
 

Dan Mills

Advanced Member level 2
Joined
Nov 10, 2013
Messages
510
Helped
239
Reputation
478
Reaction score
229
Trophy points
43
Activity points
4,558
One thing to note is that you only get about 4.5V of boost voltage (IntVcc is 5V) so the mosfets really want to be logic level.

But yea, layout, schematic and BOM please.

Regards, Dan.
 

electric1

Junior Member level 2
Joined
Apr 23, 2011
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,507
Schematic, layout and BOM attached. Please ignore the portion on the right side with MCU based data acquisition, its a separate section of the project and not even populated yet, my issue is strictly with LTC4020 portion of the project.

BOM lists important parts which I had to order, not listed some common parts I had laying around.

All FETs I tried had low RDSon specified at Vgs=4.5v , and those same FETs were listed in LTC application notes I found for this and similar ICs with 4.5v gate drivers. In fact FETs Q3 and Q4 on my board are the same ones as the demo board.

View attachment Schematic.pdf


View attachment BOM.pdf


PCB layout.JPG
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
48,427
Helped
14,252
Reputation
28,765
Reaction score
12,942
Trophy points
1,393
Location
Bochum, Germany
Activity points
280,223
I tried to make my PCB layout similar to the demo board
Does this mean, the demo board uses a two-layer PCB without thermal vias for the MOSFETs?

I also think that using 100V, 40 mohm@4.5V MOSFETs isn't the best option for 28 V input. But the converter should at least work with 2.5A output with acceptable heating, so there's probably a different problem.

In a first step I would thorougly look at switching waveforms while the load increases.
 

Dan Mills

Advanced Member level 2
Joined
Nov 10, 2013
Messages
510
Helped
239
Reputation
478
Reaction score
229
Trophy points
43
Activity points
4,558
Is it just me or is there a stupidly massive split in the ground plane between the chip and the power side particularly near the input side of the thing?

You should never route a high speed, heavy current signal over a split in its reference plane, and some of the stuff you have going on here falls into that category.

This sort of thing really needs a solid ground plane, and that usually means a 4 layer board is a much better starting point then a two layer one.

A stylistic thing, but setting the cad package to 45 degree snap and using a suitable grid snap would make some of the routing look decidedly less weird.

Regards, Dan.
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
19,772
Helped
4,350
Reputation
8,709
Reaction score
4,314
Trophy points
1,393
Activity points
130,852
Hi,

Why did you connect a capacitor to the I_Lim pin?
It's meant to use a resistor...

Klaus
 

electric1

Junior Member level 2
Joined
Apr 23, 2011
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,507
Hi,

Why did you connect a capacitor to the I_Lim pin?
It's meant to use a resistor...

Klaus

According to application notes and the schematic of the demo board there is 0.22uF cap on I_Lim pin which provides soft start function. Using resistor here would limit the inductor current, which is not my requirement.

- - - Updated - - -

Does this mean, the demo board uses a two-layer PCB without thermal vias for the MOSFETs?

I also think that using 100V, 40 mohm@4.5V MOSFETs isn't the best option for 28 V input. But the converter should at least work with 2.5A output with acceptable heating, so there's probably a different problem.

In a first step I would thorougly look at switching waveforms while the load increases.

I know that 100V FET isn't the best on the 28V input, but its just one of the FETs I tried so far because it had low Qg. I also tried 40V FETs, same ones as on the output, same results.

I will try to get scope snapshots posted here.

Demo board is 4 layers, but I never done a 4 layer board before, so I'm a bit scared to mess it up, I figured the schematic was not that complicated to do on 2 layers. Is it a fact that such device can't be done on 2 layer board? FETs on demo board don't have any thermal vias and they don't even get warm under load, only inductor gets warm on the demo board.

Is it just me or is there a stupidly massive split in the ground plane between the chip and the power side particularly near the input side of the thing?

You should never route a high speed, heavy current signal over a split in its reference plane, and some of the stuff you have going on here falls into that category.

The split was my attempt to separate analog and power ground planes, as suggested in app notes, to prevent switching currents within analog ground plane. I sunk all analog ground points at the ground plane which is split from the one where high currents flow. I never done 4 layer boards, so this was my attempt to stay with 2 layers and separate analog and power paths. Maybe I did not do it correctly, but could it explain massive overheating of FETs I am seeing? Would it be better to remove the split and merge all grounds together?
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
48,427
Helped
14,252
Reputation
28,765
Reaction score
12,942
Trophy points
1,393
Location
Bochum, Germany
Activity points
280,223
The split was my attempt to separate analog and power ground planes, as suggested in app notes, to prevent switching currents within analog ground plane. I sunk all analog ground points at the ground plane which is split from the one where high currents flow. I never done 4 layer boards, so this was my attempt to stay with 2 layers and separate analog and power paths. Maybe I did not do it correctly, but could it explain massive overheating of FETs I am seeing? Would it be better to remove the split and merge all grounds together?

I agree with Dan Mills that the ground split can bring up serious problems, mainly because it's cutting a direct ground path between the controller chip and the output stage. But it's only one of many possible problem causes.

A 40 mohm FET generates about 250 mW*duty cycle power dissipation at 2,5 A output current, which should be well managable without dedicated heat sinking. But you have also inductor ripple current which is load independent in a synchronous converter. Plus the currents cause by (too) large snubbers. I can't tell if it's still O.K. without an exact calculation.
 

Dan Mills

Advanced Member level 2
Joined
Nov 10, 2013
Messages
510
Helped
239
Reputation
478
Reaction score
229
Trophy points
43
Activity points
4,558
My take is that for a beginner, 4 layers is very much more likely to work then two, but there may well be other problems.
There is a solid reason the demo board uses 4 layers for such a relatively simple circuit.

When dealing with fast switching power supplies, the layout is the other half of the schematic, and pulling it off on two layers can take several respins even for the experienced.

In the first instance a solid plane is 9 times out of 10 a better starting point then guessing about split planes until you have way more experience.

Take some copper tape and a scalpel to your prototype and fill in that slot, I bet there are still other things, but behaviour should improve once the fet gate current doesn't have to go a mile round the houses.

Regards, Dan.
 

Lisitsin

Newbie level 2
Joined
Aug 21, 2015
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
12
Please, see R4-C8 circuit: it is heavy load to you mosfets (4,7 Ohm at switch frequency)
 

Easy peasy

Advanced Member level 5
Joined
Aug 15, 2015
Messages
3,062
Helped
1,118
Reputation
2,236
Reaction score
1,162
Trophy points
113
Location
Melbourne
Activity points
16,912
C6 may be causing current spikes in the sense resistor when the fet turns on, try making the snubbers smaller (10nF, 100V, and 10 ohm) and see if this allows the chip to provide more PWM and more power...!

- - - Updated - - -

Since your ground plane is fairly extensive it won't hurt to close the gap (with some solder braid or copper strip) every where, and see if this allows some of the sensing signals a better path to the control IC - (you can always take it off if no improvement).
 

Lisitsin

Newbie level 2
Joined
Aug 21, 2015
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
12
Did problem fixed? I make my project on LTC4020 too, but it still not work. There is no current consumption and charge process, indication STAT1.
 

Attachments

  • LTC4020 SCHEMATIC DIAGRAM.pdf
    41.9 KB · Views: 41
  • LTC4020 КРР.doc
    55.5 KB · Views: 20
  • Assembly_bottom.pdf
    10.1 KB · Views: 13
  • Assembly_top.pdf
    17.1 KB · Views: 17
  • Wires_bottom.pdf
    82.3 KB · Views: 15
  • Wires_top.pdf
    75.3 KB · Views: 18

SunnySkyguy

Advanced Member level 5
Joined
Sep 26, 2007
Messages
6,744
Helped
1,675
Reputation
3,348
Reaction score
1,644
Trophy points
1,413
Location
Richmond Hill, ON, Canada
Activity points
50,737
First you need to start verifying signals and ground noise accurately with a 150MHz scope or faster. Then calibrate two probes on the test signal in differential mode for a flat line using A+B(invert) when not using the reference ground above. e.g. Vds and solder test pins or <10mm 1/4W resistor wire (if not avail) to accommodate the probe test points. ( consider Design For Testing (DFT), next time)


proper scope measure.jpg
- verify the inputs & Outputs of each switch timing to look for deadband and shootthru between swtiches and from body diode switching off. ( using different probes) If there is evidence of shoothrough, then try to increase deadband time with asymmetric delays ( diode+RC) and reduce dv/dt which will lower interference noise coupling.

- Add ~5mm flat rolled braid wire with heatshrink where necessary to reduce inductance on high current tracks ( cheap to make) with short solid wire end. If feedback signals look and twisted pair AWG 30 magnet wire for feedback if signals look terrible and snub with 10 Ohms at a breakpoint frequency that makes sense.

- Verify the feedback using the chips ground reference pin

- The advantage of a ground plane is the distributed capacitance and L/C ratio lowers the impedance for noise immunity as well as emissions.

-Consider the mismatched impedance ratios of your transmission lines being switched in 10ns. The demo board used FETs that were much slower. (100~200ns) if I recall.
- Your RdsOn (<<50mΩ) at Vgs=4.5. much lower impedance than your inductive traces, so that's not the problem. It's timing or mismatched latency and interference. ( too fast for this design)

For reference remember that TEN (10) NANOHENRIES at 20MHz is about TWO OHMS and scale up with rise time using ~ fbw=(1/3Tr)
10nH = 2Ω @ 20MHz
Compared to RdsOn and Isense, that's alot.

High currents and excessive parasitic inductance can generate extremely fast δV/δt times during this transition. These fast δV/δt transitions can sometimes cause avalanche breakdown in the synchronous FET body diode, generating shoot-through currents via parasitic turn-on of the synchronous FET.

Layout practices and component orientations that minimize parasitic inductance on the switched nodes is critical for reducing these effects.
Ref TI datasheet.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top