# Low Frequency Oscillation in PLL Control Voltage

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#### ranran19870222

##### Newbie level 6
Hi all, I am designing a PLL at 1GHz with output tracking the input (no divider). I am using a PFD/CP with RC//C loop filter, and my VCO is a delay-line type ring oscillator. I chose a phase margin=60 degrees, damping factor zeta=1, the loop bandwidth=25MHz, and the natural frequency=10MHz.

When I went to Cadence transistor-level simulation, I could always see when the control voltage approaches the voltage required for locking (close to 0.7V in my case), it always has a low frequency ripple on it. I've attached the settling behavior of the control voltage. The ripple is about 18MHz and has a peak-peak amplitude of about 40mV.

I've tried to replace the VCO with an ideal VCO and the loop locked quietly with only high frequency ripple (frequency same as my reference) of about 1mV, so I assume the problem comes from my VCO. But my VCO works good individually as a block with a good linearity in the range of interest. I also tried to add two vcvs as buffers before and after the VCO in the PLL, but that didn't help.

I don't quite understand where the low frequency (18MHz) ripple comes from and how to solve the problem. I will appreciate if you can give any inputs or suggestions!

Faye

Here is the settling behavior of the PLL control voltage:

#### Warpspeed

Difficult to nail down, but I would suggest there is too much loop gain and insufficient phase margin at around 18 Mhz.
You may need roll it off a bit earlier and just accept a slight decrease in performance..

#### LvW

I wouldnt call it "ripple" - and I dont think the observed effect has something to do with an unsufficient phase margin.
To me, the form of the disturbance looks like a waveform which exists during the lock-in process.
Hence, my explanation: The PLL has not yet finally locked. There is something like a threshold that inhibits final locking.

- - - Updated - - -

Here is a typical VCO control voltage during lock-in:

#### Attachments

• PLL-Lock.pdf
17.1 KB · Views: 14

#### dick_freebird

A charge pumping PLL will always have some activity on Vtune
because pumped charge is quantized and has some deadband
in the phase detector. Drifts on Vtune from leakage etc. will
demand an occasional "refresh" in the best case.

Question is, is the "ripple" sinusoidal (as ought to come from
a classical stability issue) or triangular / trapezoidal (as comes
from charge impulses to a filter)?

And speaking of filter, sometimes people like to use a minimal
one to get simulations to achieve lock in tolerable "wall time"
(or simply not fail for data volume) but this is going to magnify
charge and leakage induced perturbations when obvserved as
tune voltage; is your filter end-game-realistic, or contributing
to confusion?

#### ranran19870222

##### Newbie level 6

Do you have an idea where this threshold comes from? It seems to come from the VCO since if I replace my VCO with an ideal one which has the same Kvco, the loop can lock quietly. I tried to put vcvs as buffers before and after my VCO, but it didn't help. By the way, do you know if it is the correct way to do the buffer by using vcvs?

Many thanks,
Faye

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