Xilinx says, "a path between two registers with a timing requirement that is a multiple of the clock period for the registers".
It is commonly used to relax the timing constraints in sections of your design where the data timing is relatively slow or uncertain compared to the clock rate.
Multicycle path (MCP)is a path which takes more than one clock cycle to output the data.
Setup and hold calculations will be different for MCP.
Usually multicycle path is seen in adder, multiplier design. It takes more than 1 clock cycle to update the output.
Such kind of combinational path has to be declared as multicycle path in DC(synopsys). Otherwise tool tries to optimize it and take huge amount of time and goes into loop. :?:
multicycle path comes into picture when the data lauched by a flop takes more time than the clock period itself, hence we can capture the current data in the next clock cycle. Also we can apply multicycle path if the lauch data is stable for more than one clock period therefore the capture flop dosent need to catpure the data in the next cycle it can capture it in next to next cycle.