Looking for information about multicycle path

[pradeep2323]

can anybody tell more regarding multicycle path?

 

[mcpdevs]

multi cycle path

It's nothing but a single path in the netlist activated by more than one clock domain.

 

[p_shinde]

what are multi-cycle paths

when a data takes more than one clk cycle to travel from one flop to next flop its called mutli cycle path

 

[echo47]

why multicycle path

Xilinx says, "a path between two registers with a timing requirement that is a multiple of the clock period for the registers".

It is commonly used to relax the timing constraints in sections of your design where the data timing is relatively slow or uncertain compared to the clock rate.

 

[vlsichipdesigner]

multicycle path b/w two different clocks

A detailed discussion and scenario's where multicycle paths are possible is discussed in the website more informational.

https://www.vlsichipdesign.com/static timing analysis

 

[thamarai]

multicycle path xilinx

The path, which takes more than one clock pulse to reach next flop is called as multicycle path.

 

[vasuruta]

what is multicycle path

Multicycle path (MCP)is a path which takes more than one clock cycle to output the data.
Setup and hold calculations will be different for MCP.

Usually multicycle path is seen in adder, multiplier design. It takes more than 1 clock cycle to update the output.

Such kind of combinational path has to be declared as multicycle path in DC(synopsys). Otherwise tool tries to optimize it and take huge amount of time and goes into loop. :?:

 

[chanpreet]

defining setup and hold on multicycle paths

multicycle path comes into picture when the data lauched by a flop takes more time than the clock period itself, hence we can capture the current data in the next clock cycle. Also we can apply multicycle path if the lauch data is stable for more than one clock period therefore the capture flop dosent need to catpure the data in the next cycle it can capture it in next to next cycle.

 

[Hards]

timequest multicycle

When a data path is too long that can not be completed in one clock cycle then for that perticular path we have to define mulfi-cycle path.

 

[kumar_eee]

synopsys design compiler multicycle

refer this link...

https://www.altera.com/support/software/quartus2/timequest/clock/tq-clock.html