Re: synopsys design flow
hi
thanks for ur reply.
but i want to do the improvement of below code for speed by using designware ip
but i dont know how to instantiate.
actually i want to replace highlighted line of below code with inbuild ip.
which is sum of product term and equiavlent ip is DW02_prod_sum.
so please let me know if u hv any guideline.
/ This is a simple cubic function
//
module cube( clk,reset,din,dout,waddr,wstrobe,wdata,rdata);
input clk,reset;
input [15 : 0] din;
output [15 : 0] dout;
input [ 1 : 0] waddr;
input wstrobe;
input [15 : 0 ] wdata;
output [15 : 0] rdata;
//
// This is a set of the registers...
//
reg [15 : 0] coef[0:3];
integer x;
// latch the coefficients in from the bus...
always @(posedge clk)
begin:blockc
if(reset==1) begin
coef[0]=0;
coef[1]=0;
coef[2]=0;
coef[3]=0;
x=0;
end else begin
if(wstrobe==1) coef[waddr]=wdata;
x=din;
end
end
assign rdata = coef[waddr];
wire [15:0] cf0,cf1,cf2,cf3;
reg [15:0] t1,t2,t3,t4,t5;
integer sum,c0,c1,c2,c3;
assign cf0=coef[0];
assign cf1=coef[1];
assign cf2=coef[2];
assign cf3=coef[3];
always @(posedge clk)
begin
t1<= x*x*x*cf3;
t2<= x*x*cf2;
t3<= x*cf1;
t4<= cf0;
t5<= 32'h00008000;
sum <= t1+t2+t3+t4+t5; end
assign dout = sum[31:16];
endmodule