Looking for detailed information about synopsys design flow

[alpeshchokshi]

synopsys design flow

hello friends,
i would like to know the synopsys design flow in detail.
Also what i have to do to improve the design for high speed?
can anybody explain me?
Thanks in advance

 

[gliss]

Re: synopsys design flow

For Synopsys:
VCS for VHDL/Verilog functional verification => DC for synthesis => Primetime for Timing => ICC for physical implementation => HSpice for IC simulation
I guess to improve speed or to improve the design overall you can back annotate the post-implementation physical information upstream for more accurate synethesis and placement.

 

[alpeshchokshi]

Re: synopsys design flow

hey
if i want to use the synopsys designware module to improve my speed
how can i use it?
i want to use DW02_prod_sum block

 

[yuenkit]

synopsys design flow

use
compile_ultra

let DC choose the best implementation for you.
instatiate by your own always not the best thing to do.

If you really want to do some high-speed design (small design), you will have to do custom design(analog design). For instance, RAM is high speed design, which normally done by using custom design flow.

 

[alpeshchokshi]

Re: synopsys design flow

hi
thanks for ur reply.
but i want to do the improvement of below code for speed by using designware ip
but i dont know how to instantiate.
actually i want to replace highlighted line of below code with inbuild ip.
which is sum of product term and equiavlent ip is DW02_prod_sum.
so please let me know if u hv any guideline.


/ This is a simple cubic function
//

module cube( clk,reset,din,dout,waddr,wstrobe,wdata,rdata);
input clk,reset;
input [15 : 0] din;
output [15 : 0] dout;
input [ 1 : 0] waddr;
input wstrobe;
input [15 : 0 ] wdata;
output [15 : 0] rdata;

//
// This is a set of the registers...
//
reg [15 : 0] coef[0:3];
integer x;

// latch the coefficients in from the bus...
always @(posedge clk)
begin:blockc

if(reset==1) begin
coef[0]=0;
coef[1]=0;
coef[2]=0;
coef[3]=0;
x=0;
end else begin
if(wstrobe==1) coef[waddr]=wdata;
x=din;
end
end

assign rdata = coef[waddr];

wire [15:0] cf0,cf1,cf2,cf3;
reg [15:0] t1,t2,t3,t4,t5;
integer sum,c0,c1,c2,c3;
assign cf0=coef[0];
assign cf1=coef[1];
assign cf2=coef[2];
assign cf3=coef[3];

always @(posedge clk)
begin
t1<= x*x*x*cf3;
t2<= x*x*cf2;
t3<= x*cf1;
t4<= cf0;
t5<= 32'h00008000;
sum <= t1+t2+t3+t4+t5; end

assign dout = sum[31:16];
endmodule

 

[rakko]

Re: synopsys design flow

Take a look at this document on synopsys site. It gives many example for both vhdl and verilog. Instantiating designware blocks is a little complicated. You need to do it a few times over to get comfortable with it. What makes them even more complicated is that you can pass different parameters to the models once you instantiate them to make them more suited for your design.


www.synopsys.com/products/designware/ docs/doc/dwf/datasheets/dwf_using.pdf

 

[alpeshchokshi]

Re: synopsys design flow

ya i have already browse the synopsy documentation,
but its unclear to me how to instantiate the ip?
thats is the only point i would like to ask?

 

[jjww110]

synopsys design flow

show example:
always @ (posedge count)
begin : bill // name procedure
/* synopsys resource billspecial;
map_to_module = " dw01_inc"
implement = "cla" ;
ops ="greasedincr"; */
count = count + 1;
end