long length signal wire on-chip risky?

[prcken]

Hi
I am doing layout for a >10Gbps signal. but due to practical issue the signal wire is very long in the layout (>1mm as the red arrow indicates in the uploaded picture)
Is that risky? I think it has to be treated as a transmission line now? But it seems impossible to add extra termination resistors.
Any comments?
Thanks!

 

[vfone]

I think it has to be treated as a transmission line now?

Even for less Gbps the PCB trace should be treated as a transmission line.

Anyway, I think your design it will work, but you have to simulate somehow the "Eye Test" performances.
Here you can find some plots regarding performance vs trace length at 10Gbs:

https://www.smtnet.com/library/files/upload/Considerations-for-High-Speed-PCB-Track-Design.pdf

 

[volker@muehlhaus]

Is that risky? I think it has to be treated as a transmission line now? But it seems impossible to add extra termination resistors.

Yes, it is risky. The very minimum is to extract the equivalent series L and shunt C and see what this does to your circuit performance. Extracting it as a transmission line (equivalent: distributed LC for lossless lines, RLGC for lossy lines) is more accurate to higher frequencies.

 

[prcken]

Yes, it is risky. The very minimum is to extract the equivalent series L and shunt C and see what this does to your circuit performance. Extracting it as a transmission line (equivalent: distributed LC for lossless lines, RLGC for lossy lines) is more accurate to higher frequencies.

I don't know how to extract as distributed RLGC, i think Calibre only extracts as a lumped RLC.
I will try to do extract simulation and see the eye diagram.

 

[volker@muehlhaus]

I don't know how to extract as distributed RLGC, i think Calibre only extracts as a lumped RLC.

That's correct. For more accurate modelling of critical interconnects, full wave EM solvers like Sonnet or ADS Momentum are required.

I will try to do extract simulation and see the eye diagram.

Yes, it's a good starting point.