Logic synthesis using Design Compiler

[jswan]

logic synthesis with design compiler

Hello.

I've got a problem on compiling my logic with DC. There is a 32bit x 32bit multiplier and the multiplier seems to be a critical path. I just simply described the multiplier as shown below in verilog.

input [31:0] a;
input [31:0] b;
output [63:0] c;

assign c = a * b;

'cause I'm a very beginner, there's nothing to find out in what structure DC made the multiplier. Just I'm wondering if there is any way to reduce its critical delay.

There's gotta be a way such as modifying the architecture of the multiplier, I think, if it is a booth multiplier.

In a word, is there kind of compiler directive to inform the compiler of which architecture of a multiplier a designer wants to use?

 

[eeeraghu]

design compiler multiplier

Hi,

DC uses design ware multiplier available if it sees a *, which itself has a large delay. so either use a multi cycle path between the path where multiplier is a critical path.

regards
~

 

[haneet]

logic synthesis design compiler

well evn i had the same problem..
the solution which i found was defining the design ware multiplier right in the code.
this resolved the critical path delay to a great extnt... like ealier if my slack was -0.5 then now it came to around 2...

so i hope i have reolved ur trouble.. details about the design ware can be found in google if u search.. u will also get the exact edsign ware multiplier name and other details

haneet