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Many systems use frequency hopping as a means to protect data security, avoid muti-path fading, and avoid interference. The time spent by the PLL in achieving frequency lock is valuable time that cannot be used for transmitting or receiving data; this reduces the effective data rate achievable. Currently there is no PLL available than can frequency-hop quickly enough to meet the timing requirements of the GSM protocol. In base-station applications, two separate PLL devices are used in parallel to reduce the number of wasted slots. While the first is generating the LO for the transmitter, the second PLL is moving to the next allocated channel. In this case a super-fast (<10-µs) settling PLL would significantly reduce the bill of materials (BOM) and layout complexity.
By increasing the PFD frequency. The PFD frequency determines the rate at which a comparison is made between the VCO/N and the reference signal. Increasing the PFD frequency increases the update of the charge pump and reduces lock time. It also allows the loop bandwidth to be widened.
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